gpio offset

Hello,
How do you determine the offset of the gpioxx.
#!/bin/bash
#This appears to work with fpga.bin loaded
echo "++ Exporting switches "
for i in 0 1 2 3 4 5 6 7;
do
        sw=$(($i+65));
        echo $sw > /sys/class/gpio/export;
done;

#!/bin/sh
value=0;
for i in 0 1 2 3 4 5 6 7;
do
        sw=$((72-$i));
        sw_tmp=`cat /sys/class/gpio/gpio$sw/value`;
        value=$(($value*2));
        value=$(($value+$sw_tmp));
done;
printf "0x%x %d
" $value $value;
This work with the system.ucf.
NET processing_system7_0_GPIO_pin[11]tLOC = F22 | IOSTANDARD="LVCMOS25"; # "SW0"
NET processing_system7_0_GPIO_pin[12]tLOC = G22 | IOSTANDARD="LVCMOS25"; # "SW1"
NET processing_system7_0_GPIO_pin[13]tLOC = H22 | IOSTANDARD="LVCMOS25"; # "SW2"
NET processing_system7_0_GPIO_pin[14]tLOC = F21 | IOSTANDARD="LVCMOS25"; # "SW3"
NET processing_system7_0_GPIO_pin[15]tLOC = H19 | IOSTANDARD="LVCMOS25"; # "SW4"
NET processing_system7_0_GPIO_pin[16]tLOC = H18 | IOSTANDARD="LVCMOS25"; # "SW5"
NET processing_system7_0_GPIO_pin[17]tLOC = H17 | IOSTANDARD="LVCMOS25"; # "SW6"
NET processing_system7_0_GPIO_pin[18]tLOC = M15 | IOSTANDARD="LVCMOS25"; # "SW7"

NET processing_system7_0_GPIO_pin[19]tLOC = T22 | IOSTANDARD="LVCMOS33"; # "LD0"
NET processing_system7_0_GPIO_pin[20]tLOC = T21 | IOSTANDARD="LVCMOS33"; # "LD1"
NET processing_system7_0_GPIO_pin[21]tLOC = U22 | IOSTANDARD="LVCMOS33"; # "LD2"
NET processing_system7_0_GPIO_pin[22]tLOC = U21 | IOSTANDARD="LVCMOS33"; # "LD3"
NET processing_system7_0_GPIO_pin[23]tLOC = V22 | IOSTANDARD="LVCMOS33"; # "LD4"
NET processing_system7_0_GPIO_pin[24]tLOC = W22 | IOSTANDARD="LVCMOS33"; # "LD5"
NET processing_system7_0_GPIO_pin[25]tLOC = U19 | IOSTANDARD="LVCMOS33"; # "LD6"
NET processing_system7_0_GPIO_pin[26]tLOC = U14 | IOSTANDARD="LVCMOS33"; # "LD7"
I can not get the LED to work.

Thanks

Parents

0 Former Member over 11 years ago

Hello All
My problem is that I cannot get the 8 leds to work. The 8 switches are working.
ls /sys/class/gpio/
export    gpiochip0 unexport
root@zedboard:/etc/init.d# export_sw
++ Exporting switches
root@zedboard:/etc/init.d# cat /usr/bin/export_sw
#!/bin/bash
#This appears to work with fpga.bin loaded
echo "++ Exporting switches "
for i in 0 1 2 3 4 5 6 7;
do
        sw=$(($i+65));
        echo $sw > /sys/class/gpio/export;
done;
root@zedboard:/etc/init.d# ls /sys/class/gpio/
export    gpio66    gpio68    gpio70    gpio72       unexport
gpio65    gpio67    gpio69    gpio71    gpiochip0
cat /usr/bin/read_sw
#!/bin/sh
value=0;
for i in 0 1 2 3 4 5 6 7;
do
        sw=$((72-$i));
        sw_tmp=`cat /sys/class/gpio/gpio$sw/value`;
        value=$(($value*2));
        value=$(($value+$sw_tmp));
done;
printf "0x%x %d
" $value $value;
setting the switches 10101010
root@zedboard:/etc/init.d# read_sw
0xaa 170

I recently built a system.bit and with meta-topic a fpga.bin
It appears that the fpga.bin is being loaded since I have a script
ck_fpga that I extracted from /etc/init.d/fpga-image-load.sh
#!/bin/sh
#extracted from /etc/init.d/fpga-image-load.sh
#used to check if fpga.bin was loaded.
result=`cat     /sys/devices/amba.[0123]/f8007000.devcfg/prog_done`
echo $result
root@zedboard:~# ./ck_fpga
1

I would think that 8 Leds would be 73-80.
cat /usr/bin/export_led
#!/bin/bash
#This appears to work with fpga.bin loaded
echo "++ Exporting switches "
for i in 0 1 2 3 4 5 6 7 ;
do
        led=$(($i+73));
        echo $led > /sys/class/gpio/export;
        echo out > /sys/class/gpio/gpio$led/direction;
done;
This gets errors.
Could this be the problem ZedBoard_Linux_Design net processing_system7_0_GPIO<7> LOC = T22 while the
cf_adv7511_zed uses NET processing_system7_0_GPIO_pin[11]. I have gone over this many times but can not determine the offsets needed to get the 8 Leds to work.   Any and all help is appreciated. Thanks
                                           ZedBoard_Linux_Design
system.ucf
############################
#                          #
# On-board LED's           #
#                          #
############################
net processing_system7_0_GPIO<7> LOC = T22 | IOSTANDARD = LVCMOS33;    # LD0
net processing_system7_0_GPIO<8> LOC = T21 | IOSTANDARD = LVCMOS33;    # LD1
net processing_system7_0_GPIO<9> LOC = U22 | IOSTANDARD = LVCMOS33;    # LD2
net processing_system7_0_GPIO<10> LOC = U21 | IOSTANDARD = LVCMOS33;    # LD3
net processing_system7_0_GPIO<11> LOC = V22 | IOSTANDARD = LVCMOS33;    # LD4
net processing_system7_0_GPIO<12> LOC = W22 | IOSTANDARD = LVCMOS33;    # LD5
net processing_system7_0_GPIO<13> LOC = U19 | IOSTANDARD = LVCMOS33;    # LD6
net processing_system7_0_GPIO<14> LOC = U14 | IOSTANDARD = LVCMOS33;    # LD7

############################
#                          #
# On-board Slide Switches #
#                          #
############################
net processing_system7_0_GPIO<15> LOC = F22 | IOSTANDARD = LVCMOS33;    # SW0
net processing_system7_0_GPIO<16> LOC = G22 | IOSTANDARD = LVCMOS33;    # SW1
net processing_system7_0_GPIO<17> LOC = H22 | IOSTANDARD = LVCMOS33;    # SW2
net processing_system7_0_GPIO<18> LOC = F21 | IOSTANDARD = LVCMOS33;    # SW3
net processing_system7_0_GPIO<19> LOC = H19 | IOSTANDARD = LVCMOS33;    # SW4
net processing_system7_0_GPIO<20> LOC = H18 | IOSTANDARD = LVCMOS33;    # SW5
net processing_system7_0_GPIO<21> LOC = H17 | IOSTANDARD = LVCMOS33;    # SW6
net processing_system7_0_GPIO<22> LOC = M15 | IOSTANDARD = LVCMOS33;    # SW7
GPIO
    MIO GPIO MIO
        EMIO GPIO (Width) 60
MIO 0   GPIO gpio[0] disabled
MIO 9   GPIO gpio[9] disabled
MIO 10   GPIO gpio[10] disabled
           .
           .
           .
MIO 15   GPIO gpio[15] disabled
Ports
              Connected Port
(IO_IF)GPIO_0 Connected to External Ports
              External Posts::processing_system7_0_MIO
       GPIO   External Posts::processing_system7_0_GPIO IO [59:0]
       GPIO_I                                             I [59:0]
       GPIO_O                                             O [59:0]
       GPIO_T                                             O [59:0]

                                           cf_adv7511_zed
system.ucf
NET processing_system7_0_GPIO_pin[11]    LOC = F22 | IOSTANDARD="LVCMOS25"; # "SW0"
NET processing_system7_0_GPIO_pin[12]    LOC = G22 | IOSTANDARD="LVCMOS25"; # "SW1"
NET processing_system7_0_GPIO_pin[13]    LOC = H22 | IOSTANDARD="LVCMOS25"; # "SW2"
NET processing_system7_0_GPIO_pin[14]    LOC = F21 | IOSTANDARD="LVCMOS25"; # "SW3"
NET processing_system7_0_GPIO_pin[15]    LOC = H19 | IOSTANDARD="LVCMOS25"; # "SW4"
NET processing_system7_0_GPIO_pin[16]    LOC = H18 | IOSTANDARD="LVCMOS25"; # "SW5"
NET processing_system7_0_GPIO_pin[17]    LOC = H17 | IOSTANDARD="LVCMOS25"; # "SW6"
NET processing_system7_0_GPIO_pin[18]    LOC = M15 | IOSTANDARD="LVCMOS25"; # "SW7"

NET processing_system7_0_GPIO_pin[19]    LOC = T22 | IOSTANDARD="LVCMOS33"; # "LD0"
NET processing_system7_0_GPIO_pin[20]    LOC = T21 | IOSTANDARD="LVCMOS33"; # "LD1"
NET processing_system7_0_GPIO_pin[21]    LOC = U22 | IOSTANDARD="LVCMOS33"; # "LD2"
NET processing_system7_0_GPIO_pin[22]    LOC = U21 | IOSTANDARD="LVCMOS33"; # "LD3"
NET processing_system7_0_GPIO_pin[23]    LOC = V22 | IOSTANDARD="LVCMOS33"; # "LD4"
NET processing_system7_0_GPIO_pin[24]    LOC = W22 | IOSTANDARD="LVCMOS33"; # "LD5"
NET processing_system7_0_GPIO_pin[25]    LOC = U19 | IOSTANDARD="LVCMOS33"; # "LD6"
NET processing_system7_0_GPIO_pin[26]    LOC = U14 | IOSTANDARD="LVCMOS33"; # "LD7"
GPIO
    MIO GPIO MIO
        EMIO GPIO (Width) 32
MIO 0   GPIO gpio[0] disabled
MIO 9   GPIO gpio[9] disabled
MIO 10   GPIO gpio[10] disabled
           .
           .
           .
MIO 15   GPIO gpio[15] disabled
Ports
              Connected Port
(IO_IF)GPIO_0 Connected to External Ports
       GPIO   External Posts::processing_system7_0_GPIO_pin IO [31:0]
       GPIO_I                                             I [31:0]
       GPIO_O                                             O [31:0]
       GPIO_T                                             O [31:0]
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0 Former Member over 11 years ago

Hello All
My problem is that I cannot get the 8 leds to work. The 8 switches are working.
ls /sys/class/gpio/
export    gpiochip0 unexport
root@zedboard:/etc/init.d# export_sw
++ Exporting switches
root@zedboard:/etc/init.d# cat /usr/bin/export_sw
#!/bin/bash
#This appears to work with fpga.bin loaded
echo "++ Exporting switches "
for i in 0 1 2 3 4 5 6 7;
do
        sw=$(($i+65));
        echo $sw > /sys/class/gpio/export;
done;
root@zedboard:/etc/init.d# ls /sys/class/gpio/
export    gpio66    gpio68    gpio70    gpio72       unexport
gpio65    gpio67    gpio69    gpio71    gpiochip0
cat /usr/bin/read_sw
#!/bin/sh
value=0;
for i in 0 1 2 3 4 5 6 7;
do
        sw=$((72-$i));
        sw_tmp=`cat /sys/class/gpio/gpio$sw/value`;
        value=$(($value*2));
        value=$(($value+$sw_tmp));
done;
printf "0x%x %d
" $value $value;
setting the switches 10101010
root@zedboard:/etc/init.d# read_sw
0xaa 170

I recently built a system.bit and with meta-topic a fpga.bin
It appears that the fpga.bin is being loaded since I have a script
ck_fpga that I extracted from /etc/init.d/fpga-image-load.sh
#!/bin/sh
#extracted from /etc/init.d/fpga-image-load.sh
#used to check if fpga.bin was loaded.
result=`cat     /sys/devices/amba.[0123]/f8007000.devcfg/prog_done`
echo $result
root@zedboard:~# ./ck_fpga
1

I would think that 8 Leds would be 73-80.
cat /usr/bin/export_led
#!/bin/bash
#This appears to work with fpga.bin loaded
echo "++ Exporting switches "
for i in 0 1 2 3 4 5 6 7 ;
do
        led=$(($i+73));
        echo $led > /sys/class/gpio/export;
        echo out > /sys/class/gpio/gpio$led/direction;
done;
This gets errors.
Could this be the problem ZedBoard_Linux_Design net processing_system7_0_GPIO<7> LOC = T22 while the
cf_adv7511_zed uses NET processing_system7_0_GPIO_pin[11]. I have gone over this many times but can not determine the offsets needed to get the 8 Leds to work.   Any and all help is appreciated. Thanks
                                           ZedBoard_Linux_Design
system.ucf
############################
#                          #
# On-board LED's           #
#                          #
############################
net processing_system7_0_GPIO<7> LOC = T22 | IOSTANDARD = LVCMOS33;    # LD0
net processing_system7_0_GPIO<8> LOC = T21 | IOSTANDARD = LVCMOS33;    # LD1
net processing_system7_0_GPIO<9> LOC = U22 | IOSTANDARD = LVCMOS33;    # LD2
net processing_system7_0_GPIO<10> LOC = U21 | IOSTANDARD = LVCMOS33;    # LD3
net processing_system7_0_GPIO<11> LOC = V22 | IOSTANDARD = LVCMOS33;    # LD4
net processing_system7_0_GPIO<12> LOC = W22 | IOSTANDARD = LVCMOS33;    # LD5
net processing_system7_0_GPIO<13> LOC = U19 | IOSTANDARD = LVCMOS33;    # LD6
net processing_system7_0_GPIO<14> LOC = U14 | IOSTANDARD = LVCMOS33;    # LD7

############################
#                          #
# On-board Slide Switches #
#                          #
############################
net processing_system7_0_GPIO<15> LOC = F22 | IOSTANDARD = LVCMOS33;    # SW0
net processing_system7_0_GPIO<16> LOC = G22 | IOSTANDARD = LVCMOS33;    # SW1
net processing_system7_0_GPIO<17> LOC = H22 | IOSTANDARD = LVCMOS33;    # SW2
net processing_system7_0_GPIO<18> LOC = F21 | IOSTANDARD = LVCMOS33;    # SW3
net processing_system7_0_GPIO<19> LOC = H19 | IOSTANDARD = LVCMOS33;    # SW4
net processing_system7_0_GPIO<20> LOC = H18 | IOSTANDARD = LVCMOS33;    # SW5
net processing_system7_0_GPIO<21> LOC = H17 | IOSTANDARD = LVCMOS33;    # SW6
net processing_system7_0_GPIO<22> LOC = M15 | IOSTANDARD = LVCMOS33;    # SW7
GPIO
    MIO GPIO MIO
        EMIO GPIO (Width) 60
MIO 0   GPIO gpio[0] disabled
MIO 9   GPIO gpio[9] disabled
MIO 10   GPIO gpio[10] disabled
           .
           .
           .
MIO 15   GPIO gpio[15] disabled
Ports
              Connected Port
(IO_IF)GPIO_0 Connected to External Ports
              External Posts::processing_system7_0_MIO
       GPIO   External Posts::processing_system7_0_GPIO IO [59:0]
       GPIO_I                                             I [59:0]
       GPIO_O                                             O [59:0]
       GPIO_T                                             O [59:0]

                                           cf_adv7511_zed
system.ucf
NET processing_system7_0_GPIO_pin[11]    LOC = F22 | IOSTANDARD="LVCMOS25"; # "SW0"
NET processing_system7_0_GPIO_pin[12]    LOC = G22 | IOSTANDARD="LVCMOS25"; # "SW1"
NET processing_system7_0_GPIO_pin[13]    LOC = H22 | IOSTANDARD="LVCMOS25"; # "SW2"
NET processing_system7_0_GPIO_pin[14]    LOC = F21 | IOSTANDARD="LVCMOS25"; # "SW3"
NET processing_system7_0_GPIO_pin[15]    LOC = H19 | IOSTANDARD="LVCMOS25"; # "SW4"
NET processing_system7_0_GPIO_pin[16]    LOC = H18 | IOSTANDARD="LVCMOS25"; # "SW5"
NET processing_system7_0_GPIO_pin[17]    LOC = H17 | IOSTANDARD="LVCMOS25"; # "SW6"
NET processing_system7_0_GPIO_pin[18]    LOC = M15 | IOSTANDARD="LVCMOS25"; # "SW7"

NET processing_system7_0_GPIO_pin[19]    LOC = T22 | IOSTANDARD="LVCMOS33"; # "LD0"
NET processing_system7_0_GPIO_pin[20]    LOC = T21 | IOSTANDARD="LVCMOS33"; # "LD1"
NET processing_system7_0_GPIO_pin[21]    LOC = U22 | IOSTANDARD="LVCMOS33"; # "LD2"
NET processing_system7_0_GPIO_pin[22]    LOC = U21 | IOSTANDARD="LVCMOS33"; # "LD3"
NET processing_system7_0_GPIO_pin[23]    LOC = V22 | IOSTANDARD="LVCMOS33"; # "LD4"
NET processing_system7_0_GPIO_pin[24]    LOC = W22 | IOSTANDARD="LVCMOS33"; # "LD5"
NET processing_system7_0_GPIO_pin[25]    LOC = U19 | IOSTANDARD="LVCMOS33"; # "LD6"
NET processing_system7_0_GPIO_pin[26]    LOC = U14 | IOSTANDARD="LVCMOS33"; # "LD7"
GPIO
    MIO GPIO MIO
        EMIO GPIO (Width) 32
MIO 0   GPIO gpio[0] disabled
MIO 9   GPIO gpio[9] disabled
MIO 10   GPIO gpio[10] disabled
           .
           .
           .
MIO 15   GPIO gpio[15] disabled
Ports
              Connected Port
(IO_IF)GPIO_0 Connected to External Ports
       GPIO   External Posts::processing_system7_0_GPIO_pin IO [31:0]
       GPIO_I                                             I [31:0]
       GPIO_O                                             O [31:0]
       GPIO_T                                             O [31:0]
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