Je1 GPIO - Cant seem to access upper pins

PurplePig 5 months ago

# Xilinx Zedboard (Zynq 7020) GPIO 0

I am working with a new Zedboard with the Zynq 7020 processor.

I was trying to strobe the pins on the JE1 PMOD port

To this end I defined the following pins

```

File: helloworld.c

61: int iPortPins[10];

62:

63: #define JE1 13

64: #define JE2 10

65: #define JE3 11

66: #define JE4 12

67: #define JE7 0

68: #define JE8 9

69: #define JE9 14

70: #define JE10 15

71: #define LED 7

72:

```

and configured them as follows

defined as

what I had observed as that the GPIO_0 DIRM and OEN were not allowing the GPIO 0 pins to

drive the PMOD so I explicitly set them

What I observed is I was only able to write the lower 8 bits of each of these registers.

### before

code to change **DIRM** and **OEN**

```

u32 pGPIO_0_DIRM = 0xE000A204;

Xil_Out32(pGPIO_0_DIRM, (u32)(iMask));

u32 pGPIO_0_OEN = 0xE000A208;

Xil_Out32(pGPIO_0_OEN, (u32)(iMask));

```

### after

Note that bits 8-15 were ignored.

This is also the case if I try to modify them from the ide memory window. If I write 0xffffffff only the lower 8 bits are modified.

(Both DIRM and OEN)

Why is this?

PurplePig 5 months ago

Source

/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
 * helloworld.c: simple test application
 *
 * This application configures UART 16550 to baud rate 9600.
 * PS7 UART (Zynq) is not initialized by this application, since
 * bootrom/bsp configures it to baud rate 115200
 *
 * ------------------------------------------------
 * | UART TYPE   BAUD RATE                        |
 * ------------------------------------------------
 *   uartns550   9600
 *   uartlite    Configurable only in HW design
 *   ps7_uart    115200 (configured by bootrom/bsp)
 */

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"

#include "xgpiops.h"
#include "xparameters.h"

XGpioPs_Config	*psGPIO_Config = NULL;
XGpioPs 		my_Gpio;

int				Status;
int				Status2;

int				iPortPins[10];

#define JE1		13
#define JE2		10
#define JE3		11
#define JE4		12
#define JE7		0
#define JE8		9
#define JE9		14
#define JE10	15
#define LED		7

void pause(u32 u32Pause)
{
	volatile u32 ii = 0;
	for( ii = 0; ii< u32Pause; )
	{
		ii++;
	}
}

int main()
{
	volatile u32 	ii 		= 0;
	volatile u32 	iMask 	= 0;
	int				iPinCount = 0;

	init_platform();

	iPortPins[iPinCount++] = JE1;
	iPortPins[iPinCount++] = JE2;
	iPortPins[iPinCount++] = JE3;
	iPortPins[iPinCount++] = JE4;
	iPortPins[iPinCount++] = JE7;
	iPortPins[iPinCount++] = JE8;
	iPortPins[iPinCount++] = JE9;
	iPortPins[iPinCount++] = JE10;
	iPortPins[iPinCount++] = LED;


    print("Hello World. \n\rBienvenidos!\n\r");

//	SlcrUnlock();

//	u32 pUnlock = 0xF8000008;
//    Xil_Out32(pUnlock, (u32)(0xdf0d));

//    u32 pMIO_PIN_00 = 0xF8000700;
//    Xil_Out32(pMIO_PIN_00, (u32)(0x1601));
//    Xil_Out32(pMIO_PIN_00, (u32)(0x1601));
//    Xil_Out32(pMIO_PIN_00, (u32)(0x0601));

	psGPIO_Config 		= XGpioPs_LookupConfig( XPAR_PS7_GPIO_0_DEVICE_ID );
    Status 	= XGpioPs_CfgInitialize(&my_Gpio, psGPIO_Config, psGPIO_Config->BaseAddr);

    if ((Status == 0) && (Status2 == 0))
    {

    	for (ii=0; ii < iPinCount; ii++)
    	{
    		XGpioPs_SetDirectionPin( &my_Gpio, iPortPins[ii], 1);
    		XGpioPs_WritePin( &my_Gpio, iPortPins[ii], 1);
    		iMask = iMask | (1 << iPortPins[ii]);
    	}

    	u32 pGPIO_0_DIRM = 0xE000A204;
    	Xil_Out32(pGPIO_0_DIRM, (u32)(iMask));

    	u32 pGPIO_0_OEN = 0xE000A208;
    	Xil_Out32(pGPIO_0_OEN, (u32)(iMask));

    	while(1)
    	{
	    	for (ii=0; ii < iPinCount; ii++)
	    	{
	    		XGpioPs_SetDirectionPin( &my_Gpio, iPortPins[ii], 1);
	    		XGpioPs_WritePin( &my_Gpio, iPortPins[ii], 0);
	    	}
        	pause(10000000);

	    	for (ii=0; ii < iPinCount; ii++)
	    	{
	    		XGpioPs_SetDirectionPin( &my_Gpio, iPortPins[ii], 1);
	    		XGpioPs_WritePin( &my_Gpio, iPortPins[ii], 1);
	    	}
        	pause(10000000);
    	}
    }

    print("Successfully ran Hello World application");
    cleanup_platform();
    return 0;
}

PurplePig 5 months ago

The memory Viewer was not accurate. I added a printf and hot the expected value. XSCT could not read that address.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel