# Xilinx Zedboard (Zynq 7020) GPIO 0
I am working with a new Zedboard with the Zynq 7020 processor.
I was trying to strobe the pins on the JE1 PMOD port
To this end I defined the following pins
```
File: helloworld.c
61: int iPortPins[10];
62:
63: #define JE1 13
64: #define JE2 10
65: #define JE3 11
66: #define JE4 12
67: #define JE7 0
68: #define JE8 9
69: #define JE9 14
70: #define JE10 15
71: #define LED 7
72:
```
and configured them as follows
defined as
what I had observed as that the GPIO_0 DIRM and OEN were not allowing the GPIO 0 pins to
drive the PMOD so I explicitly set them
What I observed is I was only able to write the lower 8 bits of each of these registers.
### before
code to change **DIRM** and **OEN**
```
u32 pGPIO_0_DIRM = 0xE000A204;
Xil_Out32(pGPIO_0_DIRM, (u32)(iMask));
u32 pGPIO_0_OEN = 0xE000A208;
Xil_Out32(pGPIO_0_OEN, (u32)(iMask));
```
### after
Note that bits 8-15 were ignored.
This is also the case if I try to modify them from the ide memory window. If I write 0xffffffff only the lower 8 bits are modified.
(Both DIRM and OEN)
Why is this?
