Clock for RTL Module

Question

I have a custom verilog module that I would like to provide a 100mhz clock. For the zcu102, I would normally just create a clock constraint using the si570 but I can't seem to find an equivalent on the zuboard. The constraint wizard also doesn't seem to allow for generated clocks with the zuboard. Any suggestions?

adriang · Accepted Answer

You can use a PS2PL clock, in which case constraints are being handled by the block design containing the PS. If you do a build with that and report clocks you should see it properly constrained. As far as I can tell there's no clock input to the PL from pins on the ZUBoard, so a regular pin+clock constraint in your xdc is not applicable.

adamc · Answer

That worked! Thank you adriang! 
 For those looking to do the same... 1. Go to "open block design" -> click + sign "Add IP" -> search for "ps" -> add zynq ultrascale 2. Double click "zynq ultrscale" block in design -> click "clock configuration" on left -> click "output clocks" tab -> "low power domain clocks" -> configure a new clock under "pl fabric clocks" 3. In the block design, connect the new "pl_clk0" output on "zynq ultrascale" to your RTL clock input. 4. Run synthesis and go to I/O Ports and find your clock input pin. Then right click on it and choose "autoplace io ports". I also set mine to "Fixed" after it was autoplaced, but I'm not sure that was necessary. 5. Use the "constraints wizard" to setup your clock. 6. Now you should be able to generate a bitstream. Enjoy your new clock!

Clock for RTL Module

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