The goal of this post is turn a fixed VHDL design into a configurable one. Change a fixed RAM IP into RAM that can be sized, without changing source or logic.
I use michaelkellett's VHDL RAM Memory design before: use RAM...
The Zynq family has an on-board 12 bit ADC, in the FPGA part of the silicon. They call it the XADC.It can sample internal rails and temperatures. There's also the possibility to use external inputs.In this series of 2 blogs, I'm trying to sample..…
