This is a supporting post for Part 2: Add the Accelerated IP to a Vivado design.I'm untangling the different data streams.There are 3 types of data exchanged between the FPGA and ARM parts of the Zynq:
"Business Data": the inputs and outputs to..…
I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience.
Use the Accelerated function in Software
In part 1, we made the hardwa...
I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience.
Register the IP and Use it in Vivado
In part 1, we made the hardware a...
