I am beset with a range of problems with a new design I am starting, which is to interface a HMCAD 1511 ADC with a Spartan 7 SP 701 Evaluation Board. Hopefully someone will be be able to help me make some sense of this.
I have read through the Xilinx APP, XAPP524. I propose using the HMCAD 1511 in single channel mode. Single channel mode (Fs = 1000 MSPs) requires a bit rate clock of 500 MHZ DDR. Or does it? Is this any different from dual and quad modes where according to https://www.analog.com/media/en/technical-documentation/data-sheets/hmcad1511.pdf Figures 4 through 6 it is obvious the bit clock remains the same while the input *** varies? From the point of view of interleaving then what advantage does this confer anyway if the bit clock rate reamins at 500 MHZ?As far as I can see it is just that more of the output channels have to be utilized as the sample clock increases but I would like to be enlightened.
The other confusing item is that XAPP524 makes reference to 1 wire mode and 2 wire mode. Would the HMCAD 1511 not correspond to 1 wire mode since there is apparently no let in bit clock rate as sampling frequency is relaxed? According to the calculation of XZPP524, for 8 bit, 1000 Ms/s, 1 wire ADC, the DDR bit clock is 4,000 MHZ, making this topology not feasible for the 7 series FPGAs.
Thanks if someone can share some insight into the above or describe if (s)he was successfully able to implement single channel mode with XAPP524 in a Spartan 7 FPGA.