FPGA or Microcontroller ?

It all depends on whether you want to learn embedded programming or logic design, i.e., do you want to become a software engineer, a hardware engineer, or both.  For embedded programming, you need a processor evaluation board, for example the ARM Cortex-M4 board you have listed.  You might also see if you can get an STM32F4-Discovery board.  It's inexpensive (US$20 at Newark in USA), but does not have any plug-in modules like the one you listed.  Discovery does have headers with 0.1" pin pitch.

If you want to learn logic design and design digital hardware, an FPGA module is a great platform.  Lattice Semiconductor is currently selling eval boards for their ICE40 series for US$20 plus shipping in USA.  It doesn't have any plug-in modules either, but does have 0.1" pitch headers.

Both boards are designed to be used with PCs: you edit your source code and compile on the PC and download binaries to the board over USB.

Hello AK,

From where I estimate you to be in your development as an engineer I suggest that you start with a microcontroller board. You can get an ARM Cortex M4 from ST on their Discovery board for about £10 or from TI on their new board for abpout £5. You won't get into FPGA for quite so little money. There are free tools for ARM processors.

Some good books will cost you more (a lot more) so I suggest that you look on the net for projects and examples - there are loads.

If you decide on the FPGA route the choice between Verilog and VHDL is tricky - the difference has been summed up as:

Verilog was designed by software engineers who knew nothing about hardware.

VHDL was designed by harddware engineers who knew nothing about software.

I use VHDL !

Good luck - and come back and ask specific questions when you choose a board.

Michael Kellett

Michael Kellett wrote:

 

If you decide on the FPGA route the choice between Verilog and VHDL is tricky - the difference has been summed up as:

 

Verilog was designed by software engineers who knew nothing about hardware.

VHDL was designed by harddware engineers who knew nothing about software.

IIRC, VHDL was sponsored by USA Dept of Defense as a way to describe hardware for simulation and other forms of verification.  Its purpose was to make sure you were actually designing the correct VLSI functionality.  Since is was created for USA DoD it was polite to base it on Ada, which was also sponsored by USA DoD.

IIRC, Verilog was created by a company that made automatic test equipment.  Its purpose was to create test vectors and simulate the expected behavior so it could be compared to actual chips.

Neither was created as a good language for logic synthesis.  This becomes clear when you try to use either to generate the logic you really want.

The best hardware description language I've been paid to use was Altera's AHDL.  It was very easy to tell it what logic I wanted to design, i.e., I could specify what storage elements I wanted and the equations needed to update them.  It was easy to specify async/sync preset/clear behavior, which is a PITA in Verilog/VHDL.

Hello John,

The current advice for modern FPGAs and synthesis tools is that you should concentrate on describing what you want to happen rather than the detail of the gates used to achieve it. There is also a lot of antipathy towards graphical tools. I find that you just have to look up and use 'magic' sequences in VHDL to make the tools infer things like RAM.

I've never used AHDL (confusingly the tool I use all the time is Aldec HDL which is a VHDL/Verilog simulator etc).

I suppose we can get used to not caring much about the gate level stuff, after all I don't worry much about which registers or instructions a C compiler uses.

Michael Kellett

Michael Kellett wrote:

 

The current advice for modern FPGAs and synthesis tools is that you should concentrate on describing what you want to happen rather than the detail of the gates used to achieve it. There is also a lot of antipathy towards graphical tools. I find that you just have to look up and use 'magic' sequences in VHDL to make the tools infer things like RAM.

I suppose we can get used to not caring much about the gate level stuff, after all I don't worry much about which registers or instructions a C compiler uses.

I'd be interested in hearing who gave you that advice.  When I do FPGA design, I'm trying to fit as much function as possible into as small an FPGA as possible, and to do this it helps to understand what logic is being created.  I think FPGA vendors want you to design your logic to be as inefficient as possible, so you have to buy the largest, fastest, and most expensive FPGAs.  They don't like logicians like me who use clever tricks to get by with a fraction of the logic resources.

I usually don't care about individual gates since I'm using FPGAs based on LUTs (Look-Up Tables), but I keep careful track of the number of LUTs used and sure wish the blasted Xilinx software would produce a decent textual netlist for FPGAs like it does for CPLDs.  Yes indeed, I have a lot of antipathy towards some graphical tools, particularly automatically-generated schematics (useless for non-trivial logic) and simulation waveforms (also useless for non-trivial logic).  OTOH, there are times when I'd like to be able to specify some of my logic blocks graphically.

I don't care what C generates on a high-performance PC.  I do care if I'm trying to squeeze it into a tiny microcomputer, which is what I'm doing with a small FPGA.

So what do I want an FPGA to do at the behavioral level?  Pretty simple:

S' = F(S, X)

Y = G(S, X)

where S is the current state vector, S' is the next state, X is the input vector, and Y is the output vector.  F and G are combinational expressions.  Yeah, a Mealy machine just like we leared in  logic theory. 

Michael Kellett wrote:

 

The current advice for modern FPGAs and synthesis tools is that you should concentrate on describing what you want to happen rather than the detail of the gates used to achieve it. There is also a lot of antipathy towards graphical tools. I find that you just have to look up and use 'magic' sequences in VHDL to make the tools infer things like RAM.

I suppose we can get used to not caring much about the gate level stuff, after all I don't worry much about which registers or instructions a C compiler uses.

I'd be interested in hearing who gave you that advice.  When I do FPGA design, I'm trying to fit as much function as possible into as small an FPGA as possible, and to do this it helps to understand what logic is being created.  I think FPGA vendors want you to design your logic to be as inefficient as possible, so you have to buy the largest, fastest, and most expensive FPGAs.  They don't like logicians like me who use clever tricks to get by with a fraction of the logic resources.

I usually don't care about individual gates since I'm using FPGAs based on LUTs (Look-Up Tables), but I keep careful track of the number of LUTs used and sure wish the blasted Xilinx software would produce a decent textual netlist for FPGAs like it does for CPLDs.  Yes indeed, I have a lot of antipathy towards some graphical tools, particularly automatically-generated schematics (useless for non-trivial logic) and simulation waveforms (also useless for non-trivial logic).  OTOH, there are times when I'd like to be able to specify some of my logic blocks graphically.

I don't care what C generates on a high-performance PC.  I do care if I'm trying to squeeze it into a tiny microcomputer, which is what I'm doing with a small FPGA.

So what do I want an FPGA to do at the behavioral level?  Pretty simple:

S' = F(S, X)

Y = G(S, X)

where S is the current state vector, S' is the next state, X is the input vector, and Y is the output vector.  F and G are combinational expressions.  Yeah, a Mealy machine just like we leared in  logic theory. 

@ John Beetem,

I think we are edging towards the Xilinx concept of "free silicon" - FPGA gates are pretty cheap now and almost all of the designs I do the cost of development is way higher than the total cost of the chips because the production volumes are quite low. It makes economic sense to speed up the development cycle even if that needs a bigger FPGA because the product gets to market quicker and the total cost is reduced.

I agree about auto generated schematics (never use them) but I find the Aldec Waveform viewer an essential tool. I use a block diagram editor for top level design because it automates all that loathsome VHDL needed to join things together.

Michael Kellett