Kinetis ADC Optimization
Optimal ADC performance with 16-bit accuracy requires care to minimize sources of noise on the analog supplies and grounds, the ADC reference, and the input signal itself.
Static performance
This describes ADC error when converting on a static/DC input. A ramp test can be used to get linearity values.
DNL is “code width error”, where code width is the range of input voltages, VADIN, that result in a given ADC conversion value. To determine DNL accurately, we must sweep VADIN in increments much less than 1 LSB(V) and identify transition voltages where the ADC conversion value changes from code (x-1) to code x and from code x to code (x+1). Ideally, the delta in these transition voltages = code width x = 1 LSB(V), so DNL is the difference between the actual code with and the ideal 1 LSB(V). Note that DNL is measured for one conversion code independent of all other codes.
INL is the cumulative/integrated effect of all the DNL error from conversion code 1 up to the code of interest. For test purposes, once DNL is established for all codes, INL is simply the sum of all DNLs
Dynamic performance
This describes ADC error when converting on a continuously changing input. Dynamic performance (ENOB, SNR, SINAD, THD, etc) is determined by sampling a pure sine wave input, passing the raw data through an FFT (and window function depending on the setup), and using the FFT results to determine ratios of signal to noise and/or harmonic distortion.
There is no simple, straight-forward translation between DC and AC performance parameters, though there is a correlation between them. You cannot use one set of parameters to predict the other.
In terms of software there are several configurations that will depend on the application, these are some recommendations that will improve the ADC performance
- Higher supply VREFH means larger LSB with more stable results
- Slower system-core clock rates to minimize periodic noise. If the application allows it you can sample at VLPR
- Lower ADC clock rates to allow more time for sampling and settling of comparator
- Ambient, cold temperatures are better than hot for thermal noise
- Use as much conversion averaging as allowed by sample requirements
- Long sample time is better, as it allows more time for VIN to settle
- Differential inputs buys performance because you’ll be subtracting system noise
- Avoid conversions with high speed communications i.e. DDR, USB, serial
- Perform ADC conversions in low-power modes for most “quiet” environment
Hardware
Ground and power supplies
- We strongly recommend separate regulators for digital VDD and analog VDDA supplies, though they need to set to the same level.
- No inductive coupling between VSS and VSSA
- There has been success in using isolated digital and analog planes resistively coupled (0W) at a “starpoint” directly underneath VSSA pin/ball.
- There should be two ground planes, one for digital and a second for analog.
- The board designer needs to avoid overlap of the digital ground plane with the analog ground plane
- Analog signals and analog power should remain closely coupled with the analog ground plane.
- Separate regulators for digital and analog supplies
- Even better to provide an independent regulator for VREFH
- Large “tank” caps at the regulator output for stability, decoupling caps of various values very close to the DUT. 10uF capacitors should be placed on power inputs (VDD, VDDAD, VREFH)
Inputs
- Key for 16-bit performance only
- Keep source resistance as low as possible.
- The differential inputs need to layed out in matched pairs in a side-to-side design. Ground and power planes over the analog inputs should minimize through-hole vias to provide the best possible shield over the input signals.
- Differential pair traces should be as close together as allowed for. Use VDDA and AGND to build a sort of coax shield around the signal pairs and try to separate digital signals/power/ground from analog signals/power/ground.
Differential pair 3D diagram
- For 16-bit performance, strongly consider buffering the inputs
- An input buffer and low pass filter may be necessary for some ADC modules. If the ADC input has a “kick-back” when sampling then an input buffer can reduce source impedance and source signal disruption. Caution should be used when choosing an amplifier for buffer circuit to make sure the amplifier’s specifications matches or exceeds the ADC specifications. Even a unity gain amplifier will have some gain and offset. A means for trimming the buffer should be added to circuit.
Trace routing
- Keep digital traces away from analog supply, ADC reference, and ADC inputs. This means vertically as well as horizontally (and will likely mean more layers for customer boards).
- Keep analog power and traces as short as possible
To summarize the ADC performance won’t be the optimal by just loading different software. It’s very depended to the application requirements and the amount of best practices in both hardware and software that can be adopted.
