This tutorial was extracted from Erich Styger blog http://mcuoneclipse.wordpress.com with his agreement.
Good news for everyone owning the FRDM-K20D50MFRDM-K20D50M board: I have extended the FSL_USB_Stack with USB CDC device class support for the K20D50M 
.
USB CDC Test Application with the FRDM-K20D50M
Demo Application
The demo projects is made with Processor Expert components so it can be easily copied or ported to another board:
FRDM-K20D50M USB CDC Application Components
I have created a demo application which echoes the entered text back on the console, with incrementing a counter:
USB CDC Test Application with the FRDM-K20D50M
FSL_USB_Stack with FSL_USB_CDC_Device
With just two additional Processor Expert components, it is possible to add USB CDC functionality to an existing projects in just a few minutes. See “USB Component Splitted and Updated” for architectural information. The component has now added a Kinetis K20D50 option:
Kinetis K20D50 in FSL_USB_CDC_Device Component
The FSL_USB_CDC_Device component features now an optional timeout feature. With this, it is easer to use the component in a bare-metal environment. It is using the extra ‘Timeout’ component which implements a timer based timeout to avoid stalling of the stack.
USB Clock Configuration
The most difficult part is the clock configuration. The USB block needs a 48 MHz clock to sample the 24 MHz USB signal. In the CPU component properties, I configured the System oscillator 0 to use the external 8 MHz crystal in Low power mode:
System Oscillator Settings
The MCG Is set to PEE and 48 MHz PLL output clock:
MCG Settings
It should be possible to use a 96 MHz PLL clock and then divide it down in the USB peripheral to a clock of 48 MHz. This is what I did first, and lost a lot of time, because this did not work 
. I have not investigated it further, but this is either a bug in the silicon or in Processor Expert? 48 MHz without prescaler in the USB worked.
Derived from this, the system clocks are set up like this:
System Clock Settings
In the Init_USB_OTG, the clock gate has to be enabled and the PLL/FLL clock to be used with 48 MHz:
USB Init_USB_OTG Settings
From the settings it would be possible to use a 96 MHz PLL clock and then to scale it down ot 48 MHz. However, with this my device did *not* enumerate
That’s it! The rest is just writing a small test application.
Sources
The above project/sources and last Processor Expert Components are attached to this post. The same repostitory hosts the updated FSL_USB_Stack and FSL_USB_CDC_Device Processor Expert components.
Happy CDCing
