In this blog we will look at how to improve the performance of the Cypress ADC_Differentaial_Preamplifier Starter Design included with PSoC Creator 3. With a simple addition the common mode performance of the circuit can be improved by 30dB using inexpensive components.

The Starter Design can be accessed when clicking on the “New” link on the PSoC Creator 3 start page.

This starter design has a four channel sequencing MUX connected to an ADC. Channel 1 of the MUX has a 10X gain differential amplifier, a 1X gain differential amplifier input is connected to channel 2 and single ended inputs are connected to channels 3 and 4. Opening TopDesign.cysch reveals the reference schematic.

**Understanding the design and its limitations**

This blog evaluates the circuit and provides simple alternatives to meet your needs. Once you understand the basic concepts you can adapt this circuit to do just about any measurement.

One important consideration is that the PSoC4 is a single supply system and the amplifiers and ADC are rail-to-rail. Therefore the inputs must never exceed either supply rail and the inputs must never drive the amplifier outputs above the supply rail or below ground. Channel 1 is fashioned after a classic 3-opamp instrumentation amplifier with the exception that the third amplifier isn’t needed because the ADC has a differential input with a gain of 1. Analog Devices has an excellent technical article (http://www.analog.com/static/imported-files/tech_articles/25406877Common.pdf) on this type of amplifier for those who really want to understand how the 3 amplifier instrumentation amplifiers works.

Here is the schematic from the starter design.

**Circuit Description**

Opamp_1 and Opamp_2 together with R1, R2 and Rg form a differential amplifier with a gain of 10.09. Rg sets the gain of the circuit. The maximum differential input for this circuit is 0.1V and the maximum common mode input (both inputs at the same voltage) is 2V. Changing the VRef select as shown in the next screenshot affects the maximum input voltage and common mode range. As mentioned before this circuit operates from a single power supply and the midpoint of operation is around VRef and not ground. Therefore neither input can operate below Vref. If either input goes below Vref it will cause an error as the corresponding amplifiers output will try to go below ground. Bipolar operation can be achieved by moving the opamps off of the PSoC4 but you will need bipolar power supplies and a negative reference voltage for the external opamps.

This screenshot shows the ADC_SAR_SEQ configuration dialog. You can extend the input range from 1V to 2.5V or 5V by changing the Vref select value. This blog only evaluates the circuit with the Vref set to 1V.

**Common Mode Accuracy:**

The datasheet for ADC SAR Seq shows 66dB CMRR. The resolution of the ADC is .2mV and the common mode error voltage reduces the effective resolution of the circuit to 7-bits over the entire common mode voltage range and accuracy of the circuit is 1% over the entire input range. This graph shows the common mode error voltage with no differential voltage between terminals. The maximum differential voltage is 100mV with the gain of 10. The good news is that with 1mV differential voltage the ADC will measure 10mV +/- 1mV.

CMRR also depends on matching of R1 and R2 and the ADC SAR Seq datasheet does not include resistor mismatching. With 1% resistors the worst case CMRR error of 2% or 40mV error voltage with 2V Common Mode voltage. This throws away another 3 bits of resolution so the circuit therefore has a worst case accuracy of 4bits over the entire common mode voltage range.

Traditionally, pots or matched resistors were used to adjust out common mode error. To remove any significant error due to mismatching resistors would require 0.01% or better resistors which are typically $18 and up in low quantities (http://www.newark.com/vishay-foil-resistors-vpg/y112110k0000t9r/resistor-10kohm-0-01/dp/98K0081) and require more board space. Pots are not reliable and will not track the other resistors over temperature and will therefore introduce thermal errors.

All is not lost. By use a multiplying DAC, as shown in this schematic, to compensate for resistor and other common mode error sources will improve performance by several orders of magnitude. In this circuit we are using a DAC8501 (Newark PN 38K0764) serial programmable DAC to function as a variable resistor in series with R2 such that the effective resistance is increased as the DAC code is decreased. R2 is selected such that it is equal to the nominal value (10K) minus the sum of the errors. With R1 and R2 each having up to 1% error plus the 0.5% error for the instrumentation amplifier is a total of 2.5%. Thus R2 is decreased by 2.5% and becomes 9.75K. The nearest standard 1% resistor value is 9.53K.

The accompanying graph shows that by adjusting the DAC value down, we can vary the effective resistance from 9.5K to 10.5K. For this graph the DAC code was decremented by 20 counts and resulted in 0.03% changes to the effective resistance which is more than adequate to adjust out all common mode errors for the entire circuit. The actual gain matching capability of the circuit is better than 0.0016% or 95dB CMRR which means you will get 12-bit accuracy from the ADC and not 4-bits over the entire common mode range as discussed earlier.

Thus, this circuit is more cost effective and space efficient than using precision matched resistors or pots. To calibrate the circuit start with a DAC code of 65196. If the measured value is negative increase the code by 20 counts. If the measured value is positive decrease the code by 20 counts. Repeat this process until the measured value is +/- 1 LSB. I am ordering the DAC and will be updating this blog over the next few weeks with sample code and measured results. Keep an eye on this post.

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