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| Kit Overview | Development Tools | Technical Documents | Video | Features | Kit Contents |
Overview
The Altera's DSP Development Kit DK-DSP-3SL150N DK-DSP-3SL150N Stratix
III Edition is RoHS compliant and delivers a complete digital signal processing (DSP) development environment. The kit facilitates the entire design process from design conception through hardware implementation. Design advancements and innovations, such as Programmable Power Technology and selectable core voltage, ensure that designs implemented in Stratix III FPGAs operate faster, but consume less power than previous generation Stratix devices.
With up to 7,280 KByte of enhanced TriMatrix memory and 384 embedded 18 × 18 multipliers, the on-board Stratix III device supplies internal memory while also providing I/O support for a variety of SDRAM (DDR2 or DDR3) and SRAM (QDRII or RLDRAM II) interfaces. Both DDR2 and QDRII are available on the Stratix III development board providing a high bandwidth, high-speed and low-latency solution.
The Stratix III development board is especially suitable for high-performance, logic-rich applications that require stringent signal and power integrity solutions. For example, the wireless, broadcast, and military markets require advanced signal processing techniques and very low power consumption, while also demanding flexibility and adaptability in the field.For further DSP based design productivity, the DSP Builder development tool is available separately.
Key Applicatins: Wireless, Broadcast, Military, Test and Measurement, Medical, DSP, Memory Interfaces and ASIC Prototyping.
Development Tools
Software Development Tools:
| Tool Type | Supplier | Supported Family | MPN | Description |
|---|---|---|---|---|
| IDE | Altera | ALL Altera Devices | Altera Quartus II | It's the industry's number one software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs. The Altera Quartus II software, the industry's number one software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs. Learn More |
Hardware Development Tools:
| Tool Type | Supplier | Support?ed Family | MPN | Description |
|---|---|---|---|---|
| Download Cable | Altera | ALL Altera Devices | PL-BYTEBLASTER2NPL-BYTEBLASTER2N | The ByteBlaster II enables a PC to configure or program Altera devices. The download cable drives configuration or programming data using a standard parallel printer port from the PC. |
| Download Cable | Altera | ALL Altera Devices | PL-USB-BLASTER-RCNPL-USB-BLASTER-RCN | The USB-Blaster drives configuration or programming data from the PC to configure or program Altera devices. The download cable interfaces to a standard USB PC port. |
| Download Cable | Altera | ALL Altera Devices | PL-ETH2-BLASTERPL-ETH2-BLASTER | The EthernetBlaster can receive configuration or programming data from the Ethernet network to remotely configure or program Altera devices. The communications cable connects to a standard Ethernet network port with an RJ-45 connector. |
Technical Documents
Learning Center
| Type | Description |
|---|---|
| User Guide | Altera: Quick Start Guide for DSP Development Kit, Stratix III Edition |
| User Guide | Altera: Getting Started User Guide for DSP Development Kit, Stratix III Edition |
| Reference Manual | Altera: Reference Manual for Data Conversion HSMC |
| Reference Manual | Altera: Reference Manual for Stratix III 3SL150 Development Board |
| Tutorials | Altera: Tutorials for DK-DSP-3SL150N Dev Kit |
Design Elements
| Type | Description |
|---|---|
| Schematics | |
| Layout | Altera: Layout File for DK-DSP-3SL150N Dev Kit |
| BOM | Altera: BOM File for DK-DSP-3SL150N Dev Kit |
| Application Library |
Video
Kit Features
The board features the following major component blocks:
- 1,152-pin Altera Stratix III EP3SL150F EP3SL150F FPGA in a ball-grid array (BGA) package
- 142,000 logic elements (LEs)
- 5,499 Kbits of memory
- 384 multiplier blocks
- Eight phase locked loops (PLLs)
- 16 global clock networks
- 736 user I/Os
- 1.1-V core power
- 256-pin Altera EPM2210GF256 EPM2210GF256 CPLD in a BGA package
- 1.8-V core power
- On-board memory
- 1-GByte DDR2 SDRAM DIMM
- 72-Mbit QDRII/+ SRAM
- 16-MByte DDR2 SDRAM devices
- Individually addressable
- 4-MByte SSRAM
- 64-MByte flash memory
- FPGA configuration circuitry
- MAX II CPLD and flash passive serial configuration
- On-board USB-Blaster
circuitry using the Quartus II Programmer
- MAX
- On-board clocking circuitry
- Two clock oscillators to support Stratix III device user logic
- 125 MHz
- 50 MHz
- SMA connector for external clock input and output
- Two clock oscillators to support Stratix III device user logic
- General user and configuration interfaces
- LEDs/displays:
- Eight user LEDs
- One configuration-done LED
- One transmit/receive LED (TX/RX) per HSMC interface
- One HSMC-present LED per HSMC interface
- Six Ethernet LEDs
- User Quad 7-segment display
- Power consumption display
- Push-buttons:
- User reset push-button (CPU reset)
- Four general user push-buttons
- System reset push-button (user configuration)
- One factory push-button switch (factory configuration)
- DIP switches:
- MAX II control DIP switch
- Eight user DIP switches
- Speaker header
- LEDs/displays:
- Displays
- 128 × 64 graphics LCD
- 16 × 2 line character LCD
- Power supply
- 14-V – 20-V DC input
- On-board power measurement circuitry
- Up to 20 W per HSMC interface
- Mechanical
- 7 in. × 8.25 in. board
- Bench-top design
Kit Contents
The Altera DK-DSP-3SL150NDK-DSP-3SL150N Stratix III DSP Development Kit supplied with below contents:
- Stratix III development board
- Data conversion high-speed mezzanine card (HSMC)
- MATLAB/Simulink 30-day evaluation software
- Power supplies and Cables
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