Altera: Introduction to The QUARTUS II Software

Overview

The Altera Quartus II software, the industry's number one software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs. Quartus II software delivers support for the latest 28-nm devices – the Arria V and Cyclone V devices – as well as enhancements to the Stratix V device support. Plan for success with System Console, a unique debug and monitoring solution. Other features include some enhancements to Qsys and a look at how software and hardware co-design will be enabled with the ARM-based system-on-a-chip (SoC) devices.

The Altera Quartus II design software provides a complete, multiplatform design environment that easily adapts to your specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes solutions for all phases of FPGA and CPLD design. In addition, the Quartus II software allows you to use the Quartus II graphical user interface and command-line interface for each phase of the design flow. You can use one of these interfaces for the entire flow, or you can use different options at different phases.

Featuring System Console is scalable, hardware debug and monitoring tool in Quartus II software. It provides an easy way to build GUI elements and connect them to hardware so that you can monitor performance, debug designs, and demonstrate design functionality. You can also debug your design anytime – in the lab, during simulation, or after the product has been shipped.

Simulation and system-level tools integrated with Quartus II software design flow are  as follows:

• ModelSim software
• DSP Builder (requires additional license)
• Qsys

The Qsys system integration tool saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys is the next-generation SOPC Builder tool powered by a new FPGA-optimized network-on-a-chip (NoC) technology, delivering higher performance, improved design reuse, and faster verification compared to SOPC Builder.

Quartus II software delivers superior synthesis and placement and routing, resulting in compilation time advantages and compilation time reduction using following features:

• Multiprocessor support
• Rapid Recompile
• Incremental compile

• An average of 25 percent faster compilation
• Improvements in multicore compilation support
• Fitter improvements that unlock the fastest silicon performance in the industry
• Higher logic packing capability than our nearest competitor
• Production release of the Altera SDK for OpenCL
• Enhancements to the Qsys system integration tool, including:
• Support for the ARM TrustZone technology plus Advanced Peripheral Bus (APBTM) and High-Performance Bus (AHBTM)
• Support for VHDL bus functional models (BFMs)
• Enhancements to Transceiver Toolkit, including:
• Bit error checking for Stratix V FPGAs
• Ability to measure and report the data rates of each active transceiver channel
• Enhancements to the SignalTapTM II logic analyzer, including:
• Ability to change basic trigger operations without recompiling
• Cross-triggering from an Altera SoC hard processor system (HPS) event
• Programmer Object File (POF) support for most 28 nm devices
• Simplified process for upgrading IP cores
• Simplified software and device family installation with the new installer

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Altera download cables are available for use in the in-circuit reconfiguration of Altera FPGAs. Download cables are also available for use in the in-system programming of MAX II, MAX 3000A, and MAX 7000 devices. With Altera download cables, design changes can be downloaded directly to the device, prototyping is easy and multiple design iterations can be accomplished in quick succession.

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Learning Center

Design Elements

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