Altera: DK-DEV-5M570ZN MAX V CPLD Development Kit

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Overview

The Altera MAX V CPLD Development Kit DK-DEV-5M570ZNDK-DEV-5M570ZN is a complete design environment that includes both the hardware and software you need to prototype the most common CPLD applications, including I/O expansion, interface bridging, power management control, initialization control, and analog interface control. The RoHS-compliant board, and the license-free Quartus II Web Edition software provide everything you need to begin developing custom MAX V CPLD designs.

The MAX V family of low cost and low power CPLDs offer more density and I/Os per footprint versus other CPLDs. Ranging in density from 40 to 2,210 logic elements (LEs) (32 to 1,700 equivalent macrocells) and up to 271 I/Os, MAX V devices provide programmable solutions for applications such as I/O expansion, bus and protocol bridging, power monitoring and control, FPGA configuration, and analog IC interface.

The following list describes what you can accomplish with the kit:

Develop designs for the multiProductLinkmultiProductLinkmultiProductLink5M570Z CPLD.
Measure CPLD power (VCCINT and VCCIO).
Bridge between two different I/O voltages.
Interface to external functions or devices via four connectors.
Read and write to memories:
- 8-Kbit (Kb) user flash memory (UFM) available within the multiProductLinkmultiProductLinkmultiProductLink5M570Z CPLD.
- I2C or SPI EEPROMs (user installed).
Come up to speed quickly with your CPLD design by reusing the example designs provided.
Re-use the kit’s PCB board and schematic as a model for your design.

Key Applications: I/O expansion, Interface bridging, Power management control, Configuration and initialization control, Analog control.

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Development Tools

Software Development Tools:

Tool Type	Supplier	Supported Family	MPN	Description
IDE	Altera	ALL Altera Devices	Altera Quartus II	It's the industry's number one software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs. The Altera Quartus II software, the industry's number one software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs. Learn More

Hardware Development Tools:

Tool Type	Supplier	Support?ed Family	MPN	Description
Download Cable	Altera	ALL Altera Devices	PL-BYTEBLASTER2NPL-BYTEBLASTER2N	The ByteBlaster II enables a PC to configure or program Altera devices. The download cable drives configuration or programming data using a standard parallel printer port from the PC.
Download Cable	Altera	ALL Altera Devices	PL-USB-BLASTER-RCNPL-USB-BLASTER-RCN	The USB-Blaster drives configuration or programming data from the PC to configure or program Altera devices. The download cable interfaces to a standard USB PC port.
Download Cable	Altera	ALL Altera Devices	PL-ETH2-BLASTERPL-ETH2-BLASTER	The EthernetBlaster can receive configuration or programming data from the Ethernet network to remotely configure or program Altera devices. The communications cable connects to a standard Ethernet network port with an RJ-45 connector.

Technical Documents

Learning Center

Type	Description
User Guide	Altera: User Guide For DK-DEV-5M570ZN Kit
User Manual	Altera: Reference Manual For DK-DEV-5M570ZN Kit
Product Brief	Altera: Product Brief For DK-DEV-5M570ZN Kit
Datasheet	Altera: Datasheet for MAX V Device Handbook
Datasheet	Altera: Datasheet on DC and Switching Characteristics for MAX V Devices
Application Note	Altera: In-System Programmability Guidelines
Research Standard	Altera: MAX V PowerPlay Early Power Estimator
Product Brief	Altera: Product Brief for MAX V Device Family

Design Elements

Type	Description
Schematics	Altera: Schematics File for DK-DEV-5M570ZN - MAX V Development Kit
Layout	Altera: Layout File for DK-DEV-5M570ZN - MAX V Development Kit
BOM	Altera: BOM File for DK-DEV-5M570ZN - MAX V Development Kit

Video

Kit Features

Low-cost, low-power, and non-volatile CPLD architecture
Instant-on (0.5 ms or less) configuration time
Standby current as low as 25 μA and fast power-down/reset operation
Fast propagation delay and clock-to-output times
Internal oscillator
Emulated RSDS output support with a data rate of up to 200 Mbps
Emulated LVDS output support with a data rate of up to 304 Mbps
Four global clocks with two clocks available per logic array block (LAB)
User flash memory block up to 8 Kbits for non-volatile storage with up to 1000 read/write cycles
Single 1.8-V external supply for device core
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels
Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per pin)
I/Os are fully compliant with the PCI-SIG PCI Local Bus Specification, revision 2.2 for 3.3-V operation
Hot-socket compliant
Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990

Kit Contents

The MAX V CPLD Development Kit (DK-DEV-5M570ZN) includes the following Contents:

RoHS-compliant MAX V development board
- MAX V CPLD (5M570Z, 256-pin FBGA, -5 speed)
- Configuration via embedded USB-BlasterTM circuitry (JTAG)
- 10-MHz single-ended, external oscillator clock source
- Shunt resistors (probe points to measure CPLD power)
- One capacitive touch-sense user-defined button
- Two user-defined push buttons
- Two user-defined LEDs
- Connectors:
  - Two general-purpose 2x20-pin 0.1-inch expansion headers
  - 4-pin PC speaker header
  - Two 6-pin motor control headers
  - Type B USB connector (power source and communication port)
  - USB cable included
  - Footprints for user to install an I2C serial EEPROM or SPI EEPROM
Designs examples:
- Board Test System (BTS)
- User I/Os
- Capacitive touch-sense
- UFM
- EEPROM
- Internal oscillator
- PC speaker
Complete documentation
- Quick start guide, user guide, reference manual, bill of materials, schematic, and board files