Freescale: DSP56800E Family Overview

Overview

The DSP56800E core architecture represents the next step in the evolution of Freescale’s 16-bit DSP56800 Family of digital signal controllers. It provides low-cost, low-power, mid-performance computing, combining DSC power and parallelism with MCU-like programming simplicity. The DSP56800E core is a general-purpose central processing unit, designed for both efficient digital signal processing and a variety of controller operations.

A powerful multiply-accumulate (MAC) unit, with optional rounding and negation, enables the efficient coding of DSC and digital filtering algorithms. The DSP56800E’s large register set, powerful addressing modes, and bit-manipulation unit allow traditional control tasks to be performed with ease, without the complexity and limitations normally associated with DSCs. Assisting in the coding of general-purpose programs is support for a software stack; flexible addressing modes; and byte, word, and long-word data types.

The DSP56800E Family is not a custom IC designed for a particular application; it is designed as a general-purpose DSC architecture to efficiently execute common DSC algorithms and controller code in minimal time.

The key attributes of a DSC are as follows:

• Multiply-accumulate (MAC) operation
• Fetching up to two operands per instruction cycle for the MAC
• Flexibility in implementation through a powerful instruction set
• Input/output capability to move data in and out of the DSC

The multiply-accumulate (MAC) operation is the fundamental operation used in DSC. The DSP56800E family of processors has a dual Harvard architecture that is optimized for MAC operations. Figure 1-5 shows how the DSP56800E architecture matches the shape of the MAC operation. The two operands, C() and X(), are directed to a multiply operation, and the result is summed. This process is built into the chip in that two separate data memory accesses are allowed to feed a single-cycle MAC. The entire process must occur under program control to direct the correct operands to the multiplier and to save the accumulated result, as needed. Since the memory and the MAC are independent, the DSC can perform two memory moves, a multiply and an accumulate, and two address updates in a single operation. As a result, many DSC benchmarks execute very efficiently for a single-multiplier architecture.

Ultra-Low Power

Kinetis MCUs feature the best in low power innovation, including ten flexible low-power operating modes for power profile optimization, power and clock gating, back-biasing, 4 μS wake up times, flash programming and analog peripheral operation down to 1.71V. The result is Stop and Run currents of <500 nA and <200μA/MHz respectively. A low-power RTC and low-leakage wake-up unit add further low power flexibility, while a low-power timer enables continual system operation in reduced power states.