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EAGLE User Chat (English) DRC rules for specific board area or chip
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Related

DRC rules for specific board area or chip

cosborne2000
cosborne2000 over 14 years ago

Is there any way to create different DRC rules for specific areas or chips on a board?

 

For example, I would like to setup a large width on the ground net but this trace needs to neck down to connect to various chips.

Fine pitch devices also require a narrow trace width to connect.

 

Currently I have to approve all the errors on the fine pitch devices but is there a more efficient way?

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  • e14 Contributor
    e14 Contributor over 14 years ago

    cosborne2000 <communitymanager@premierfarnell.com> wrote:

    Is there any way to create different DRC rules for specific areas or chips on a board?

     

    For example, I would like to setup a large width on the ground net but

    this trace needs to neck down to connect to various chips.

    Fine pitch devices also require a narrow trace width to connect.

     

    Currently I have to approve all the errors on the fine pitch devices but

    is there a more efficient way?

     

     

    Have a look at classes.

     

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  • e14 Contributor
    e14 Contributor over 14 years ago

    cosborne2000 <communitymanager@premierfarnell.com> wrote:

    Is there any way to create different DRC rules for specific areas or chips on a board?

     

    For example, I would like to setup a large width on the ground net but

    this trace needs to neck down to connect to various chips.

    Fine pitch devices also require a narrow trace width to connect.

     

    Currently I have to approve all the errors on the fine pitch devices but

    is there a more efficient way?

     

     

    Have a look at classes.

     

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  • cosborne2000
    cosborne2000 over 14 years ago in reply to e14 Contributor

    Maybe there's a section I'm missing.

     

    For example: I want a 12 width/12 clearance rule for the GND net but I need an exception for the neck down on fine pitch or BGA packages.

    Is there any way I can avoid all the DRC errors that occur at the chip?

    If I set for the tighter rules for the chip then this rule applies to the whole board.

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