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Related

SMD specs

autodeskguest
autodeskguest over 17 years ago

With much help from the support forum I'm finally getting pretty good at

creating libraries. One thing is bothering me a bit, though, and I thought

maybe the topic might generate some comments here in this chat forum. Not

being an Eagle related problem, I figured this was a better forum for this

topic.

 

When creating smd device libraries I've noticed that sometimes the

dimensions given for smd and case size, when carefully followed, would

result in the device pins being slightly off of the pads. This is not always

so, though! Sometimes the pins will be nearly perfectly centered on the

smd's. When I made inquiry to one manufacture why pins were both on and off

the pads when their dimensions were faithfully followed, I was told in

writing that the smd dimensions were "nominal" (i.e. approximate) and that

it was permissible for the smd's to be up to 15% smaller than the device

case pins and so yes, this could happen and it was allowed. I was also

pointed at small print that said somewhat the same thing in the spec. The

fudge was that same small print indicated smd's should, for the device in

question, be the same total dimension as the case (an RK73H series size 2B

device by KOA). But the the case actually overlapped by, yes, 15% when I

followed the recommended smd dimensions. All this was buried on page 69 of a

larger pdf file, by the way.

 

Well, I've worked in manufacturing for a few decades and one thing I know,

especially when lead free soldering is involved, is that increasing the

amount of solder on smd's greatly impacts warranty returns due to

temperature and vibration environmental issues that cause cracks to appear

in small solder joints. Now, I'm old school where in college they taught me

that solder is never to be used to secure a part, that a mechanical securing

method is to be used instead (this was before smd came along, though I guess

glue is supposed to be the strength when it comes to smd and it's not just

for securing the part for soldering purposes). Also, I know that lead free

solder is harder to make flow properly, thus more subject to cold soldering

problems, and that it's more brittle than is solder that contains lead. I'm

not making a case for lead, I want it out of the environment too, I'm just

voicing what I've come to know over decades.

 

So why would manufactures create landing specs knowing that maximum contact

(i.e. strength) is being compromised when all available solder area is not

being used? Sounds like a warranty nightmare to me.

 

 

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  • tpelectronics
    tpelectronics over 17 years ago

    I am agree with you lead free has some compromise to do.

    I am working very close with production line and was "lucky" to make a lot

    test of pad for SMD for lead free.

    I will not se at it is the solution for all because it is not after the

    standard IPC 7351 but I see it become more like my own experience.

     

    1)    pasta area --> done around so much you can. (with eagle you can to it

    with DRC setup, I make a special DRC setup for make the stencil

    informasjon).

        Why around pad :

                                a) lead free not flow and square form not is

    usefule

                                b) it is better for stencil to not "holde" pasta

    when you remove it.

    2)  Yes reduce the area . How much not very sure but like you write 15% it

    is not stupide at all. But when you need big pad. make a lot of small pasta

    areal than a big one. Because lead freak not flow god ,a big areal + a lot

    of pasta will holde the component form the board and the small parts will be

    very bad soldering join.

     

    3) use fresh pasta! expensive but better than resolde by hand!

     

    Thierry

     

    "RGM" <NoSpam@UseForum.please> skrev i melding

    news:gfl9qp$l0o$1@cheetah.cadsoft.de...

    With much help from the support forum I'm finally getting pretty good at

    creating libraries. One thing is bothering me a bit, though, and I thought

    maybe the topic might generate some comments here in this chat forum. Not

    being an Eagle related problem, I figured this was a better forum for this

    topic.

     

    When creating smd device libraries I've noticed that sometimes the

    dimensions given for smd and case size, when carefully followed, would

    result in the device pins being slightly off of the pads. This is not

    always so, though! Sometimes the pins will be nearly perfectly centered on

    the smd's. When I made inquiry to one manufacture why pins were both on

    and off the pads when their dimensions were faithfully followed, I was

    told in writing that the smd dimensions were "nominal" (i.e. approximate)

    and that it was permissible for the smd's to be up to 15% smaller than the

    device case pins and so yes, this could happen and it was allowed. I was

    also pointed at small print that said somewhat the same thing in the spec.

    The fudge was that same small print indicated smd's should, for the device

    in question, be the same total dimension as the case (an RK73H series size

    2B device by KOA). But the the case actually overlapped by, yes, 15% when

    I followed the recommended smd dimensions. All this was buried on page 69

    of a larger pdf file, by the way.

     

    Well, I've worked in manufacturing for a few decades and one thing I know,

    especially when lead free soldering is involved, is that increasing the

    amount of solder on smd's greatly impacts warranty returns due to

    temperature and vibration environmental issues that cause cracks to appear

    in small solder joints. Now, I'm old school where in college they taught

    me that solder is never to be used to secure a part, that a mechanical

    securing method is to be used instead (this was before smd came along,

    though I guess glue is supposed to be the strength when it comes to smd

    and it's not just for securing the part for soldering purposes). Also, I

    know that lead free solder is harder to make flow properly, thus more

    subject to cold soldering problems, and that it's more brittle than is

    solder that contains lead. I'm not making a case for lead, I want it out

    of the environment too, I'm just voicing what I've come to know over

    decades.

     

    So why would manufactures create landing specs knowing that maximum

    contact (i.e. strength) is being compromised when all available solder

    area is not being used? Sounds like a warranty nightmare to me.

     

     

     

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  • autodeskguest
    autodeskguest over 17 years ago

    "TP Electronics" <tp@tpelectronics.no> wrote in message

    news:gfltqn$j0f$1@cheetah.cadsoft.de...

    I am agree with you lead free has some compromise to do.

    I am working very close with production line and was "lucky" to make a lot

    test of pad for SMD for lead free.

    I will not se at it is the solution for all because it is not after the

    standard IPC 7351 but I see it become more like my own experience.

     

    1)    pasta area --> done around so much you can. (with eagle you can to

    it with DRC setup, I make a special DRC setup for make the stencil

    informasjon).

       Why around pad :

                               a) lead free not flow and square form not is

    usefule

                               b) it is better for stencil to not "holde"

    pasta when you remove it.

    2)  Yes reduce the area . How much not very sure but like you write 15% it

    is not stupide at all. But when you need big pad. make a lot of small

    pasta areal than a big one. Because lead freak not flow god ,a big areal +

    a lot of pasta will holde the component form the board and the small parts

    will be very bad soldering join.

     

    3) use fresh pasta! expensive but better than resolde by hand!

     

    Thierry

     

    Yes. I found that increasing pad size as much as possible, and not just for

    small pitch, and insisting that the stencil allow for as much solder as

    possible in practice, reduced warranty returns dramatically when it came to

    lead free solder stressed by vibration and temperature changes. Of course

    that made routing more difficult when it came to traces going between pads,

    increasing needed via's. Before doing that, and when going by manufacture's

    pad landing recommendations, after a year in the field the returns would

    show cracking of lead free solder joints had occurred. The problem just went

    away, nearly 100%, by getting as much solder as possible on the part leads.

    The improvement in warranty returns was truly dramatic.

     

    I never use square pads. The sharp pointed edges tend to radiate RF

    harmonics even at low applied frequencies and it's hard to cover the entire

    pad with solder, solder seems to flow much better when using rounded pads. I

    round to about 33%.

     

    But too much paste seemed to result in the part "floating around the pads"

    during the soldering process, leading to slight registration (alignment)

    issues. This wasn't much of nor was it a consistent problem, though, but

    very occasionally the part might float slightly off a pad. I don't know if

    glue was used during the soldering stage and I just don't know enough about

    the process to understand if glue should even be used with reflow and/or

    wave methods. Seems to me glue would only be used with FT, not with SMD.

     

    Serendipity! This issue has long been a problem and has come to the

    attention of the JEDEC regulatory body. Only hours after I started this

    topic I received email from JEDEC. I'll quote it here:

    ---

    JEDEC/IPC International Conferences on Lead Free Electronics

    March 4-6, 2009, Santa Clara, CA

     

    The change to lead free solder has raised issues on the manufacture,

    processing, and reliability of electronic products.

     

    IPC and JEDEC are seeking speakers to participate in a conference dedicated

    to lead-free and related issues.

    Exhibition opportunities are also available.

     

    For additional information on the program, exhibition and participation

    details, please visit:

    http://www.pb-free.org/IPC_JEDEC%20CFP%20LF%20March%202009.pdf

    ---

    The issues they wish to address are comprehensive (to be expected of JEDEC,

    of course).

     

     

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