I would like to have a 3.3V polygon on an inner layer under my processor
within a larger 5V polygon.
The 5V polygon covers the 3.3V polygon.
Is there a way toforce the 5V polygon to keep a clearance from the 3.3V
polygon?
I would like to have a 3.3V polygon on an inner layer under my processor
within a larger 5V polygon.
The 5V polygon covers the 3.3V polygon.
Is there a way toforce the 5V polygon to keep a clearance from the 3.3V
polygon?
Doug wrote:
I would like to have a 3.3V polygon on an inner layer under my processor
within a larger 5V polygon.
The 5V polygon covers the 3.3V polygon.
Is there a way toforce the 5V polygon to keep a clearance from the 3.3V
polygon?
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