The training video, "Hierarchical Design Capabilities in Eagle v7", goes a long ways towards introducing the topic. I do not think that an ERC was run after creating and connecting of modules on the top level in the video. I am getting the error, "Port GND (pwr) not compatible with pins on net within module".
I created the GND port exactly like the video. I would love a suggestion on how to make GND work and pass ERC from module to top sheet. (V+ and others are the same. GND is a good start.)
The Module pins connected to GND are: 7 passive pins, 1 in pin, 1 i/o pin, 2 pwr pins. -- One or more of these pins are being called "not compatible".
In electronic circuitry, these are all legitimate connections.
Wrestling Match #1:
I am getting, "Port GND (pwr) not compatible with pins on net within module" for my v7 Module. New thing: I removed the GND in the Module, the net called itself N$2, I changed this to GND (Label name) and the error above went away. New thing --> the N$2 matched a net on the top surface and set all of the N$2 net values to GND, but not the pins on top N$2 net. I did not want any top level nets to change their value. THE PROBLEM--> the Module used the next available Module net (N$2) and immediately confused it (combined it) with the top level N$2 -- thus, making a big mess on the top level N$2. I was able to backspace out of that tragedy (Thank Heavens). So there needs separation on net names for different levels.
Thank you for any assistance.