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dual footprint package

lblythen

I know this is a pretty common requirement. I need a part with a dual footprint so, say, the board will have a land pattern for a SOIC package and another nearby for the same part in TSOP. Whichever package is available soonest and cheapest gets soldered to the board; the pads for the alternative package are left unused.

 

This means the matching pads must be connected - CS# to CS#, Vcc to Vcc and so on. I've read ways of keeping Eagle happy by showing two symbols on the schematic, one with a SOIC package and the other TSOP, and connecting the matching pins. I don't want to do that. I want to show a single symbol whose library package has both footprints, with matching pads connected by copper in the library package.

 

First off this doubles the number of pads: a 28-lead device needs only 28 pins but would have 56 pads. I've solved that by choosing a single 'active' pad from each pair: the first becomes, say, P$1 and is connected to the relevant pin in the symbol. Its mate, for the alternative footprint, is replaced by what looks like a pad but is just a copper rectangle: a lead can be soldered to it, but it's not an SMD so Eagle isn't confused. This gives a single, 28-pin symbol on the schematic; a package in the library with 28 'active' pads; and a dual footprint with 56 lands that can be soldered to.

 

My problem is connecting the matching pads of each pair. Some of the tracking is tricky, so having routed it once I want to library the package and forget it. In the package editor it seems simple: draw wires in layer Top, to connect each active pad with its matching copper rectangle for the other footprint. But I've read that Eagle won't recognise wires in layer Top as tracks - that the autorouter will subsequently scribble 'real tracks' on top of them.

 

An alternative I've read of involves using polygons and copper pour to define each 'track', instead of the wire tool. That prevents interference by the autorouter when the package is later dropped into a board, but it's a huge job: creating polygon boundaries to mimic an intricate arrangement of 6mil tracks and copper rectangles. Even if I did it, the Eagle manual warns against defining polygons with very fine lines - I'm worried about whether a fab house would have problems making the board.

 

Has anyone solved this as I'm trying to - i.e. without resorting to two schematic symbols, each with a separate footprint? It seems much the neatest solution but I'm not sure it's achievable.

 

(Finally: I know there are implications for paste stencils and for extracting the BOM, and electrical issues such as crosstalk and the placement of bypass caps. I'm interested in solving the package-drawing problem first.)

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    Element 14 User wrote on Sun, 06 November 2011 03:08

    I've read ways of keeping Eagle happy by showing two symbols on the

    schematic, one with a SOIC package and the other TSOP, and connecting the

    matching pins. I don't want to do that.

     

    But that's the right way.  You really have two separate parts tied

    together, which should be shown on the schematic.  This way it's properly

    documented, they each get their own component designator, their own BOM

    entry, and you have flexibility routing the connections.  For something as

    complicated as tying two IC packages together, I wouldn't want the routing

    pre-determined in the package.  This needs to be determined uniquely each

    instance depending on what you are doing with the ground, which lines are

    sensitive, etc.

     

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

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  • 0

    Element 14 User wrote on Sun, 06 November 2011 03:08

    I've read ways of keeping Eagle happy by showing two symbols on the

    schematic, one with a SOIC package and the other TSOP, and connecting the

    matching pins. I don't want to do that.

     

    But that's the right way.  You really have two separate parts tied

    together, which should be shown on the schematic.  This way it's properly

    documented, they each get their own component designator, their own BOM

    entry, and you have flexibility routing the connections.  For something as

    complicated as tying two IC packages together, I wouldn't want the routing

    pre-determined in the package.  This needs to be determined uniquely each

    instance depending on what you are doing with the ground, which lines are

    sensitive, etc.

     

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

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  • 0 in reply to e14 Contributor

    Olin Lathrop wrote:

     

    Element 14 User (L B) wrote on Sun, 06 November 2011 03:08

    I've read ways of keeping Eagle happy by showing two symbols on the

    schematic, one with a SOIC package and the other TSOP, and connecting the

    matching pins. I don't want to do that.

     

    But that's the right way.  You really have two separate parts tied

    together, which should be shown on the schematic.

    Thanks for your comment. In fact if there's anything I "really have" not - never ever - it's what you describe: two separate parts tied together. The closest it comes to that is that there are two separate sets of copper pads tied together. I hoped I'd made clear that there's only ever a part soldered to one of them. Whether two parts should appear on the schematic in such cases is an interesting debate which goes to the heart of what schematics actually are. It began long before I started on electronics in the '70s and I don't imagine we'll resolve it here, but I've opened a new thread "Dual footprint - schematic representation" where it's on-topic. Here, it isn't: my topic here is whether Eagle can do what I asked, the way I asked, and if so how.