I have this problem with two PCB designs where I accidently set my layers up as ((1*2)+(15*16)) instead of (1+2+15+16) under Design Rules/Layers.
Instead of generating just one .drd file, it now generates 3 different ones (.drd.0102, .drd0116, .drd.1516) even though I set my layers back to (1+2+15+16).
I am using Eagle version 6.4.