Special Clearance Around Hole

On 7/2/2010 2:29 PM, Michael Sansom wrote:

Got an issue I haven't been able to resolve.  I've got an internal layer

that is carrying AC mains voltage (120VAC here). I have pin through hole

parts that have pins that do not connect to this layer. I need to have

35mils (0.035") of clearance between the plated hole and the interior

layer carrying this AC mains voltage, but this amount of clearance is

undesirable on other plated holes on the board. How do I treat the

plated holes on these parts which pierce this high voltage plane

differently that my default holes?

>

Thanks,

>

Michael

first of all, it's very strange to have a 120VAC plane but I guess you

have a good reason to do it.

if your plane is really a polygon, you can just draw it around the area

to avoid or place copper of a diferent name around the area to force it

to isolate. In v4, I don't know of a restrict layer for internal

polygons, but maybe v5 has such. you may also be able to define the

"penetrating" pins net names with a higher clearance value to keep the

polygon off of them in the class list, this might even work if it's a

true $plane.

Gary Gofstein schrieb:

On 7/2/2010 2:29 PM, Michael Sansom wrote:

>> Got an issue I haven't been able to resolve.  I've got an internal layer

>> that is carrying AC mains voltage (120VAC here). I have pin through hole

>> parts that have pins that do not connect to this layer. I need to have

>> 35mils (0.035") of clearance between the plated hole and the interior

>> layer carrying this AC mains voltage, but this amount of clearance is

>> undesirable on other plated holes on the board. How do I treat the

>> plated holes on these parts which pierce this high voltage plane

>> differently that my default holes?

>>

first of all, it's very strange to have a 120VAC plane but I guess you

have a good reason to do it.

That's also my first thought - I'd really try to avoid this.

if your plane is really a polygon, you can just draw it around the area

to avoid or place copper of a diferent name around the area to force it

to isolate. In v4, I don't know of a restrict layer for internal

polygons, but maybe v5 has such.

Both versions don't have restriction layers for inner layers.

you may also be able to define the

"penetrating" pins net names with a higher clearance value to keep the

polygon off of them in the class list, this might even work if it's a

true $plane.

Using different classes and their distance matrix surely seems to be the

best way.

Tilmann

"Tilmann Reh" <usenet2007nospam@autometer.de> wrote in message

news:i0nchl$6nj$1@cheetah.cadsoft.de...

>> you may also be able to define the

>> "penetrating" pins net names with a higher clearance value to keep the

>> polygon off of them in the class list, this might even work if it's a

>> true $plane.

>

Using different classes and their distance matrix surely seems to be the

best way.

I would do the dirty way: draw a circle with 0 width  around that pin, on

the inner layer.

Gary Gofstein wrote:

On 7/2/2010 2:29 PM, Michael Sansom wrote:

>> Got an issue I haven't been able to resolve.  I've got an internal layer

>> that is carrying AC mains voltage (120VAC here). I have pin through hole

>> parts that have pins that do not connect to this layer. I need to have

>> 35mils (0.035") of clearance between the plated hole and the interior

>> layer carrying this AC mains voltage, but this amount of clearance is

>> undesirable on other plated holes on the board. How do I treat the

>> plated holes on these parts which pierce this high voltage plane

>> differently that my default holes?

>>

>> Thanks,

>>

>> Michael

first of all, it's very strange to have a 120VAC plane but I guess you

have a good reason to do it.

 

if your plane is really a polygon, you can just draw it around the area

to avoid or place copper of a diferent name around the area to force it

to isolate. In v4, I don't know of a restrict layer for internal

polygons, but maybe v5 has such. you may also be able to define the

"penetrating" pins net names with a higher clearance value to keep the

polygon off of them in the class list, this might even work if it's a

true $plane.

In fact, it is not a plane it is a polygon.  I've got a portion of the

board (4 layer) that is free of internal planes and I have U.L. spacing

requirements that basically force some 120VAC tracks to the internal

layers (can't meet creepage requirements on the outer layers).  However,

due to relatively high current requirements I need as much

cross-sectional copper area as possible, so I really don't want to hand

draw the polygon around these holes as I probably won't do as good a job

as the auto-clearance.  So, adjusting the clearance would be ideal.

I'll look at the constraint matrix.

As an aside, it would be nice to just have the ability to click on a

part and set a manual clearance that would override the default.

Thanks,

Michael

eSilviu schrieb:

>> Using different classes and their distance matrix surely seems to be the

>> best way.

 

I would do the dirty way: draw a circle with 0 width  around that pin, on

the inner layer.

That's really dirty: it produces invalid gerber output.

Tilmann

Michael Sansom schrieb:

So, adjusting the clearance would be ideal.

I'll look at the constraint matrix.

It'll surely do what you need.

As an aside, it would be nice to just have the ability to click on a

part and set a manual clearance that would override the default.

For the whole part? I think using classes and their distances is much

more versatile (provided the 8 possible classes are enough for your design).

Tilmann

"Tilmann Reh" <usenet2007nospam@autometer.de> wrote in message

news:i0npcs$n43$1@cheetah.cadsoft.de...

eSilviu schrieb:

>

>>> Using different classes and their distance matrix surely seems to be the

>>> best way.

>>

>> I would do the dirty way: draw a circle with 0 width  around that pin, on

>> the inner layer.

>

That's really dirty: it produces invalid gerber output.

>

Tilmann

Yes, I've forgot that a circle with 0 width mean a filled circle in Eagle.

So do-it with minimum allowable width (0.1 . 0.2mm)

And remember: best solutions come from lazy people.

eSilviu schrieb:

>>> I would do the dirty way: draw a circle with 0 width  around that pin, on

>>> the inner layer.

>>

>> That's really dirty: it produces invalid gerber output.

 

Yes, I've forgot that a circle with 0 width mean a filled circle in Eagle.

So do-it with minimum allowable width (0.1 . 0.2mm)

 

And remember: best solutions come from lazy people.

Not always (though this is a nice statement ).

Particular in cases like this, I would strongly recommend to do it the

"correct" way.

(I am lazy enough to have thought about this method, too - but then

refused to provide that as hint for the OP... )

Using classes and their clearances also is much less work, as soon as

more than one alien pad/via is concerned.

Tilmann

"Tilmann Reh" <usenet2007nospam@autometer.de> wrote in message

news:i0nvnr$f0g$1@cheetah.cadsoft.de...

Using classes and their clearances also is much less work, as soon as

more than one alien pad/via is concerned.

but you must first learn to use this feature (netclasses), and this take

time.... for 1 pad I will not learn anything. all that matters is a working

PCB