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Eagle clearance error

Former Member

Hi,

 

I am developing a product using nrf51822. While pcb designing I am getting a clearance error. Please let me know how to resolve it. All the dimensions are 8mil in clearance tab. Can i edit this to clear the drc error?

thanks in advance.

  • Hi! Sorry in advance if I don't understand your question correctly.

     

    I am assuming here you are using the QFN package and the clearance error is between the pads of the QFN.

     

    You sure can edit the design rules to clear this error, but here is what editing the design rules mean. It means you have a fabrication house that will be able to handle a clearance of less than 8 mils. A quick check on the datasheet of your chip tells me you would need a minimum clearance of 5.9 mils. This is not an uncommon requirement. A PCB fabrication house I like to use is dirty PCBs. They actually give you design rules for their house for Eagle. And the clearance is 5 mils.

     

    Hope this helps you. Good luck with your design!

     

    Olivier

  • in reply to Former Member

    Hi Olivier,

    Thank you for the quick reply. I am new to hardware design. I am referring some online tutorial to do the design. I have seen your design rules. But am not sure how to use it in my design. Could you please explain ?

     

    thank and regards,

    rahul

     

     

  • Can you attach a screenshot of the issue.

    Possibly you may have some via for thermal relief that are causing issues.

  • in reply to ipv1

    Hi,

    PFA.

    The all error in this is related to the nrf 51 ic only. Its having clearance and width error.In eagle all the clearance dimensions are 8mil.

     

     

    image

  • in reply to Former Member

    Hi Rahul

    I think you have to look at the package informations of your U1 ic. You can find the distance between its pads. Lets say it would be 0.20mm (0.0078 in) . Then go to left menu of PCB layout and click DRC. Click clearance tab and input 0.19mm to pads. If it doesnt work probably the distance of package in eagle may be different. Try your numbers.

  • in reply to Former Member

    I think the better solution is to use an appropriate design rules file which lines up with the capabilities of the board manufacturer you are using. You can then selectively approve any remaining violations like the ones talked about here if you are sure that your board manufacturer won't have any issues. If you routinely alter design rules to clear errors then you might get bitten down the line when it masks a real issue and you don't deal with it because there was no DRC error. At least if you have to approve it you have to think about it. I had posted on this thread on this topic but for some reason those posts have disappeared.

  • in reply to rachaelp

    Yes i also think like that. But i thought Rahul has a board manufacturer that is capable to do that. If the manufacturer cant handle the precision of the U1 IC s pinout the project (at least the one with U1) is completly over.