Whats happening with EagleCad & Cadsoft?

On 07/23/11 09:54, davem wrote:

...

I would like to know ( from the horses mouth if possible) what is Cadsoft

...

We normally don't speak publicly about things that haven't been

implemented yet, but here are the things I can say so far:

...

Q2) Are we going to have a proper user definable /properly integrated BOM

window ?

Generating the BOM is apparently something every user has his own

idea about how to do it. No matter what "integrated" BOM window we

would implement, there would certainly always we someone who wants

things differently. That's what the User Language is for. You can

implement your very own, custom built BOM generator that outputs

exactly what you want, and how you want it. The bom.ulp that comes

with EAGLE can be used as a starting point, or you can choose from

several BOM ULPs in our User Files download area.

Q3) Can CUT, COPY&  PASTE ( and selection/group) work just like any other

application?

As of version 6, the COPY command will (silently) put a copy of the

current group into the system's clipboard. There will be no more CUT

command in the menus, because that has caused some irritation in the past

(of course the CUT command is still available from the command line, and

there is a SET parameter to restore the old behavior). By putting the

copy into the system's clipboard instead of a buffer internal to EAGLE,

you can then also COPY/PASTE between different instances of EAGLE.

...

Q6) Are their any plans for some sort of SChematic/Layout hierarchy or

SUB-Circuits feature.

It will be possible to paste from a consistent board/schematic file pair

into the current project by entering the file name in the PASTE command

(i.e. "paste from file"). This will also be possible via drag&drop.

That way you can easily and consistently fetch various pre-routed building

blocks into your project.

...

Q11) Are there any plans for more control over pads/holes in the device

editor? i.e Odd/Complex shapes.

This is what's currently being implemented. Any wires in signal layers that

are connected to a pad, and any polygons in signal layers that contain a

pad, will be handled as part of that pad.

...

The Beta Test forum is VERY QUIET

That's because there is currently no beta test going on.

Klaus Schmidinger

--

_______________________________________________________________

Klaus Schmidinger                       Phone: +49-8635-6989-10

CadSoft Computer GmbH                   Fax:   +49-8635-6989-40

Pleidolfweg 15                          Email:   kls@cadsoft.de

D-84568 Pleiskirchen, Germany           URL:     www.cadsoft.de

_______________________________________________________________

On 07/23/11 09:54, davem wrote:

...

I would like to know ( from the horses mouth if possible) what is Cadsoft

...

We normally don't speak publicly about things that haven't been

implemented yet, but here are the things I can say so far:

...

Q2) Are we going to have a proper user definable /properly integrated BOM

window ?

Generating the BOM is apparently something every user has his own

idea about how to do it. No matter what "integrated" BOM window we

would implement, there would certainly always we someone who wants

things differently. That's what the User Language is for. You can

implement your very own, custom built BOM generator that outputs

exactly what you want, and how you want it. The bom.ulp that comes

with EAGLE can be used as a starting point, or you can choose from

several BOM ULPs in our User Files download area.

Q3) Can CUT, COPY&  PASTE ( and selection/group) work just like any other

application?

As of version 6, the COPY command will (silently) put a copy of the

current group into the system's clipboard. There will be no more CUT

command in the menus, because that has caused some irritation in the past

(of course the CUT command is still available from the command line, and

there is a SET parameter to restore the old behavior). By putting the

copy into the system's clipboard instead of a buffer internal to EAGLE,

you can then also COPY/PASTE between different instances of EAGLE.

...

Q6) Are their any plans for some sort of SChematic/Layout hierarchy or

SUB-Circuits feature.

It will be possible to paste from a consistent board/schematic file pair

into the current project by entering the file name in the PASTE command

(i.e. "paste from file"). This will also be possible via drag&drop.

That way you can easily and consistently fetch various pre-routed building

blocks into your project.

...

Q11) Are there any plans for more control over pads/holes in the device

editor? i.e Odd/Complex shapes.

This is what's currently being implemented. Any wires in signal layers that

are connected to a pad, and any polygons in signal layers that contain a

pad, will be handled as part of that pad.

...

The Beta Test forum is VERY QUIET

That's because there is currently no beta test going on.

Klaus Schmidinger

--

_______________________________________________________________

Klaus Schmidinger                       Phone: +49-8635-6989-10

CadSoft Computer GmbH                   Fax:   +49-8635-6989-40

Pleidolfweg 15                          Email:   kls@cadsoft.de

D-84568 Pleiskirchen, Germany           URL:     www.cadsoft.de

_______________________________________________________________

Hi Klaus,

Thanks for the reply,

I have been teaching myself the scripting language and I have been playing

around with the BOM.ulp, I am learning, but it does take some time to get

familiar with this.

I like the fact you are implementing some kind of SUB-CIRUITS feature,

Thanks!

Re; PADS, So you are saying that currently I can draw "polygons" and

"wires" inside a part definition so long as they "TOUGHT a pad?, I shall

check this out, What about VIA'S for polygon heatsinks?

Thanks

Dave M

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

On 07/26/11 09:43, davem wrote:

...

Re; PADS, So you are saying that currently I can draw "polygons" and

"wires" inside a part definition so long as they "TOUGHT a pad?

I assume you mean "TOUCH"?!

A wire in a package drawing will be considered electrically

connected to a pad/smd if one of its end points coincides

with the center of the pad/smd. These need to be the exact

same coordinates.

A polygon in a package drawing will be considered electrically

connected to a pad/smd if the center of the pad/smd is inside

the area defined by the center lines of the polygon wires.

What about VIA'S for polygon heatsinks?

Vias can only be part of a signal, not a package.

However, in version 6 it will be possible to connect any number

of pads to a single pin. Sou you could draw your polygon in such

a way that it includes all the pads you want to have as part

of your heatsink, and in the device connect all these pads to

the same pin. The polygon will initially be considered electrically

connected to only one pad (whichever comes first in the data structure),

but the multiple-pad-to-one-pin connection in the device will

make them all one large electrically connected object.

Klaus Schmidinger

--

_______________________________________________________________

Klaus Schmidinger                       Phone: +49-8635-6989-10

CadSoft Computer GmbH                   Fax:   +49-8635-6989-40

Pleidolfweg 15                          Email:   kls@cadsoft.de

D-84568 Pleiskirchen, Germany           URL:     www.cadsoft.de

_______________________________________________________________

Klaus Schmidinger wrote:

On 07/23/11 09:54, davem wrote:

>> ...

>> Q6) Are their any plans for some sort of SChematic/Layout hierarchy or

>> SUB-Circuits feature.

 

It will be possible to paste from a consistent board/schematic file pair

into the current project by entering the file name in the PASTE command

(i.e. "paste from file"). This will also be possible via drag&drop.

That way you can easily and consistently fetch various pre-routed building

blocks into your project.

 

Getting back to Dave's question, will there be a schmematic hierarchy in

the next release? A while ago you guys said there would be. Is it still

planned?

I think that's very important since large companies won't buy Eagle

without a hierarchy, you can't do large projects properly without that.

In that case I'd upgrade as well. But I am not going to ask "When are we

there?"

--

Regards, Joerg

http://www.analogconsultants.com/

Klaus Schmidinger wrote:

..........We normally don't speak publicly about things that haven't been

implemented yet, but here are the things I can say so far:.............

 

................This is what's currently being implemented. Any wires in

signal

layers that are connected to a pad, and any polygons in signal layers

that contain a pad, will be handled as part of that pad.

It has been declared that the Power layers will be dispensed with and all

inner copper layers will be regular signal layers.

It has been said that pads will now be enhanced with polygon and wire

extensions, thus making irregular shaped pads possible. I assume that SMD

are included.

For the through hole PAD this raises the question of the requested feature

'Pad stack'. Will there be Pad Stack functionality to specify pad dimension

for the inner layers and  for each outer layer seperately, for a library

package?  This part needs to ignore DRC restring settings. (likely only for

the outer layers as internal layers will likely be meeting an 'internal

layer standard' based on drill size).

Thanks

Warren

On 08/02/11 01:47, Warren Brayshaw wrote:

Klaus Schmidinger wrote:

 

>> ..........We normally don't speak publicly about things that haven't been

>> implemented yet, but here are the things I can say so far:.............

>>

>> ................This is what's currently being implemented. Any wires in

signal

>> layers that are connected to a pad, and any polygons in signal layers

>> that contain a pad, will be handled as part of that pad.

>

It has been declared that the Power layers will be dispensed with and all

inner copper layers will be regular signal layers.

It has been said that pads will now be enhanced with polygon and wire

extensions, thus making irregular shaped pads possible. I assume that SMD

are included.

Yes, this applies to SMDs as well.

For the through hole PAD this raises the question of the requested feature

'Pad stack'. Will there be Pad Stack functionality to specify pad dimension

for the inner layers and  for each outer layer seperately, for a library

package?  This part needs to ignore DRC restring settings. (likely only for

the outer layers as internal layers will likely be meeting an 'internal

layer standard' based on drill size).

You will be able to draw wires and polygons for pads in any signal

layer.

Klaus Schmidinger

--

_______________________________________________________________

Klaus Schmidinger                       Phone: +49-8635-6989-10

CadSoft Computer GmbH                   Fax:   +49-8635-6989-40

Pleidolfweg 15                          Email:   kls@cadsoft.de

D-84568 Pleiskirchen, Germany           URL:     www.cadsoft.de

_______________________________________________________________

Klaus Schmidinger wrote:

...............You will be able to draw wires and polygons for pads in any

signal

layer........................

 

Klaus Schmidinger

--

Hmmm! How will thermals and be applied when a pad/SMD has been enlarged to a

custom shape?

Will a polygon pour, on the board, keep away from and create thermals to the

total custom shape or only the initial pad/SMD object?

Warren

>>Warren Brayshaw wrote:

Klaus Schmidinger replied:

>> For the through hole PAD this raises the question of the requested

>> feature 'Pad stack'. Will there be Pad Stack functionality to

>> specify pad dimension for the inner layers and  for each outer layer

>> seperately, for a library package?  This part needs to ignore DRC

>> restring settings. (likely only for the outer layers as internal

>> layers will likely be meeting an 'internal layer standard' based on

>> drill size).

 

You will be able to draw wires and polygons for pads in any signal

layer.

Greetings

Unfortuately your reply does not answer the question. "Pad Stack

functionality--defining the pad diameter of any layer, singly"?

I can interpret from what has been said:

1) that we will be able to make odd shaped pads. Or more correctly add

copper around a specified standard pad.

2) this can be done on all signal layers

3) an SMD pad can be virtually unliited in size (irrelevant for this

discussion)

Currently the restring diameter for all layers of a PTH pad is modified by

the DRC setting. If the DRC setting is not to effect a single layer then the

package pad setting will effect all layers.

The DRC setting effects the whole board so any special cases must be taken

care of in the definition of the package.

For a custom part one may wish to set all layers to'as per library' or

alternately custom the outer layers and have inner layers follow the DRC

requirements for the board.

So I feel the 'seed pad' diameter settings  need to exist for the outer

layers and one for the inner layers.

There are design cases where a large pad is needed on one side of a PCB but

the other side needs the mnimum annulus, just enought to satisfy

manufacturing for a PCB with through hole plating.

For a double sided PCB it can be a requirement of no annulus around the hole

on one outer layer, for voltage clearance reasons.

I hope the above has ben considered in the implementation under development.

Ragards

Warren

On 08/04/11 01:43, Warren Brayshaw wrote:

Klaus Schmidinger wrote:

 

>

>> ...............You will be able to draw wires and polygons for pads in any

signal

>> layer........................

>>

>> Klaus Schmidinger

>> --

 

Hmmm! How will thermals and be applied when a pad/SMD has been enlarged to a

custom shape?

Will a polygon pour, on the board, keep away from and create thermals to the

total custom shape or only the initial pad/SMD object?

It will consider the total shape of the polygon used to

enlarge the pad/smd. The polygon pour will keep away from the total

custom shape, and will create thermals accordingly.

Note that if you attach a wire to the pad in the package, that

wire will not be subtracted from the polygon (of the same

signal). It will be handled as if it had been drawn in the board.

Klaus Schmidinger

--

_______________________________________________________________

Klaus Schmidinger                       Phone: +49-8635-6989-10

CadSoft Computer GmbH                   Fax:   +49-8635-6989-40

Pleidolfweg 15                          Email:   kls@cadsoft.de

D-84568 Pleiskirchen, Germany           URL:     www.cadsoft.de

_______________________________________________________________

On 08/04/11 02:17, Warren Brayshaw wrote:

>>> Warren Brayshaw wrote:

>> Klaus Schmidinger replied:

>>> For the through hole PAD this raises the question of the requested

>>> feature 'Pad stack'. Will there be Pad Stack functionality to

>>> specify pad dimension for the inner layers and  for each outer layer

>>> seperately, for a library package?  This part needs to ignore DRC

>>> restring settings. (likely only for the outer layers as internal

>>> layers will likely be meeting an 'internal layer standard' based on

>>> drill size).

>>

>> You will be able to draw wires and polygons for pads in any signal

>> layer.

 

Greetings

Unfortuately your reply does not answer the question. "Pad Stack

functionality--defining the pad diameter of any layer, singly"?

 

I can interpret from what has been said:

1) that we will be able to make odd shaped pads. Or more correctly add

copper around a specified standard pad.

2) this can be done on all signal layers

3) an SMD pad can be virtually unliited in size (irrelevant for this

discussion)

 

Currently the restring diameter for all layers of a PTH pad is modified by

the DRC setting. If the DRC setting is not to effect a single layer then the

package pad setting will effect all layers.

The DRC setting effects the whole board so any special cases must be taken

care of in the definition of the package.

For a custom part one may wish to set all layers to'as per library' or

alternately custom the outer layers and have inner layers follow the DRC

requirements for the board.

So I feel the 'seed pad' diameter settings  need to exist for the outer

layers and one for the inner layers.

 

There are design cases where a large pad is needed on one side of a PCB but

the other side needs the mnimum annulus, just enought to satisfy

manufacturing for a PCB with through hole plating.

For a double sided PCB it can be a requirement of no annulus around the hole

on one outer layer, for voltage clearance reasons.

 

I hope the above has ben considered in the implementation under development.

Time permitting, we are planning to make a long requested change

to how the pad diameters are handled. Only pads that actually have

a zero diameter will then be adjusted automatically to the design rules,

and all others will have whatever diameter they are given. This, together

with the possibility to draw copper polygons in a package to enlarge pads,

should allow you to define pads of any shape and size.

Klaus Schmidinger

--

_______________________________________________________________

Klaus Schmidinger                       Phone: +49-8635-6989-10

CadSoft Computer GmbH                   Fax:   +49-8635-6989-40

Pleidolfweg 15                          Email:   kls@cadsoft.de

D-84568 Pleiskirchen, Germany           URL:     www.cadsoft.de

_______________________________________________________________