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Option to make tPlace (and other documentation layers) obey tStop (and tKeepout, tRestrict)

e14 Contributor

Would it be posible for Cadsoft in a future release to allow users to specify that tPlace (being generated into topsilk gerber) to honor / obey tStop. My manager that handles our board house communications is concerned about the part libraries going right over the top of the part pads. We look at tPlace and tCopper gerbers and notice that the silks generate over the pads and he doesnt want that. My only option at this point is to go in and copy every part that does this into our custom library and edit the part manually. An option in the board layout or cam processor to make all layers follow tStop / tKeepout / tRestrict would be nice. Thanks.

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  • in reply to e14 Contributor

    Ok. Guess I wont worry about it or remake many of the parts to our "specs". Thanks for the info.

  • Quote:

    Would it be posible for Cadsoft in a future release to allow users to

    specify that tPlace (being generated into topsilk gerber) to honor / obey

    tStop.

     

    Just about every board house already does this automatically, so there is

    little reason for Eagle to do it too.

     

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    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

  • "hal.hockersmith" <communitymanager@premierfarnell.com> wrote in message

    news:968105418.6101316010598408.JavaMail.jive@flcspu-csapp-01.premierfarnell.com...

    Would it be posible for Cadsoft in a future release to allow users to

    specify that tPlace (being generated into topsilk gerber) to honor / obey

    tStop. My manager that handles our board house communications is concerned

    about the part libraries going right over the top of the vias. We look at

    tPlace and notice that the silks go over the pads and he doesnt want that.

    My only option at this point is to go in and copy every part that does

    this into our custom library and edit the part manually. An option in the

    board layout or cam processor to make all layers follow tStop / tKeepout /

    tRestrict would be nice. Thanks.

     

    Eagle doesnt support this now, but a DRC will warn you if you got the tPlace

    layers active when running it.

    A decent pcb manucaturer can mask out this with his tools, but you may have

    to tell them to do it, so they get released from the responsibility if

    something important is masked out (like a refdes or label you need).

    Alternatively you just need to make sure there is no conflict when you make

    your library. Usually your board has relatively few unique device

    footprints, so editing them shouldn't take all day.