DRC is not detecting a violation - 2 files [1/1]

Thiago <thiago_hr@yahoo.com.br> wrote:

In article <j4touq$vnu$1@cheetah.cadsoft.de>,

warrenbrayshaw@paradise.net.nz says...

>>

>> Thiago wrote:

>>

>>> Yes, they are the same signals (GND), and the clearance to same

>>> signals are set to 0 (to skip overlap errors, since I have some vias

>>> over pads). But I set to 4 mils the clearance to same signals and it

>>> is still not generating errors. Weird.

>>

>> There is no check between vias of the same signal name, only between SMD and

>> SMD,PAD,VIA

>>

>> HTH

>> Warren

 

I see. So, between vias I should take care about the clearance

"manually" ?

This is a problem issue in Eagle. Especially on HDI layouts where the

manufacturer has much better quality control an issues like that can lead

to lower lifetime because it can cause leftover chemicals in the manuf

process, or issues that optical inspection will trigger on.

I dont know the reason for having same net vias that close, but merging

them with a wide wire may help you out. The problem is that Eagle doesnt

warn you about them.

In article <j4touq$vnu$1@cheetah.cadsoft.de>,

warrenbrayshaw@paradise.net.nz says...

 

Thiago wrote:

 

Yes, they are the same signals (GND), and the clearance to same

signals are set to 0 (to skip overlap errors, since I have some vias

over pads). But I set to 4 mils the clearance to same signals and it

is still not generating errors. Weird.

 

There is no check between vias of the same signal name, only between SMD and

SMD,PAD,VIA

 

HTH

Warren

I see. So, between vias I should take care about the clearance

"manually" ?

Regards,

Thiago wrote:

Yes, they are the same signals (GND), and the clearance to same

signals are set to 0 (to skip overlap errors, since I have some vias

over pads). But I set to 4 mils the clearance to same signals and it

is still not generating errors. Weird.

There is no check between vias of the same signal name, only between SMD and

SMD,PAD,VIA

HTH

Warren

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In article <j4ruvg$kot$1@cheetah.cadsoft.de>,

warrenbrayshaw@paradise.net.nz says...

 

Thiago wrote:

Hello,

 

I have set the clearance to 4 mils in all DRC fields, since this is

the minimum required from PCB house. I have attached 2 pictures, one

of them is showing a distance of only 2 mils (grid set to 1 mil)

between 2 vias that wasn?t captured by the DRC. On the other picture

there are the DRC configs.

Why is this happening? It should have detected the error on the

clearance.

 

Regards,

 

Thiago

 

Perhaps the signal names of  those two vias the same?

Your 4mil settings only apply to different signals

 

 

Warren

Yes, they are the same signals (GND), and the clearance to same signals

are set to 0 (to skip overlap errors, since I have some vias over pads).

But I set to 4 mils the clearance to same signals and it is still not

generating errors. Weird.

Thiago wrote:

Hello,

 

I have set the clearance to 4 mils in all DRC fields, since this is

the minimum required from PCB house. I have attached 2 pictures, one

of them is showing a distance of only 2 mils (grid set to 1 mil)

between 2 vias that wasn?t captured by the DRC. On the other picture

there are the DRC configs.

Why is this happening? It should have detected the error on the

clearance.

 

Regards,

 

Thiago

Perhaps the signal names of  those two vias the same?

Your 4mil settings only apply to different signals

Warren

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