"Warren Brayshaw" <warrenbrayshaw@paradise.net.nz> wrote in message
news:jamn9u$q4t$1@cheetah.cadsoft.de...
Pepe wrote:
>> Hello, thanks for your answer!
>> This is a 2 layer board, all components are placed on top, and all
>> errors of this kind are on layer 1.
>> The full space between the capacitors pads is highlighted but not the
>> pads themselves. Another similar example is an SOT143B package, while
>> both libraries were taken from Cadsoft. Another interesting case is a
>> USB mini receptacle with 5 identical, equally spaced smd pads (self
>> made) and Eagle seems to be complaining only about one pair of them
>> (see attachment).
>> The error message is in the usual dialog box, it says "Error (121) -
>> Clearance" layer 1.
>> All edit boxes in the Clearance tab of DRC are set to 0.2 mm (9 x 0,2
>> mm) and all problematic areas are larger/wider.
>> I also tried changing the clearance settings to unrealistically small
>> values (e.g: 9 x 0.01 mm) but the number of errors and the errors
>> themselves (highlighted space too) remained unchanged.
>> Any idea/suggestion?
>> Pepe
>
As well as the DRC clearances on DRC/Clearance you need to check the
clearance requirements of NET CLASSES. If they are larger than the DRC
setting the DRC will use those values.
It appeared that this was the case, so maybe Eagle should differentiate the
clearance errors messages from global DRC settings vs class settings.