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EAGLE User Support (English) polygons and component pads
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Related

polygons and component pads

e14 Contributor
e14 Contributor over 14 years ago

I frequently like to use polygons to expand the heatsink (tab area) on

parts such as D2PAK's.  Even with with isolate set to 0 and the tab

connected to the same net, there is still a small gap there.  I then go

back with a trace to manually fill in the gap.  Is there a better way to

do this?

 

Thanks

 

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  • e14 Contributor
    e14 Contributor over 14 years ago

    Hi John

     

    There should be no problem achieving what you desire without the need to

    fill the gap, if done correctly.

     

    A little short of information in your post.

     

    Which Eagle version are you using?

    Is your D2PAK a package you created or one from an Eagle library, so we can

    check how the package is constructed?

    i.e. Is the tab in the library package made from a single SMD pad  or a

    polygon with or without a smaller SMD pad?

     

    While DRC is interpreted as Design Rule Check it does dynamically modify

    the board design, in real time.

     

    The image attached shows the two situations where the signal name and the

    polygon name are the same or different.

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    On 2/29/2012 3:31 PM, Warren Brayshaw wrote:

    Hi John

     

    There should be no problem achieving what you desire without the need to

    fill the gap, if done correctly.

     

    A little short of information in your post.

     

    Which Eagle version are you using?

    Is your D2PAK a package you created or one from an Eagle library, so we can

    check how the package is constructed?

    i.e. Is the tab in the library package made from a single SMD pad  or a

    polygon with or without a smaller SMD pad?

     

    While DRC is interpreted as Design Rule Check it does dynamically modify

    the board design, in real time.

     

    The image attached shows the two situations where the signal name and the

    polygon name are the same or different.

     

    I copied LM2937 from the linear.lbr into my own library.  Since the tab

    did not have a pin connection on the schematic symbol, I added one.  In

    the symbol, I named pin 1 GND@1 and for the tab I called it GND@2.

     

    The polygon has a name of GND, with isolate set to 0.  I even tried

    setting the "same signal" clearances in DRC to 0.  Nothing seems to

    work.  It looks like the picture on the right that you sent with the

    little gap.

     

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    On 2/29/2012 3:54 PM, John Friede wrote:

    On 2/29/2012 3:31 PM, Warren Brayshaw wrote:

    >> Hi John

    >>

    >> There should be no problem achieving what you desire without the need to

    >> fill the gap, if done correctly.

    >>

    >> A little short of information in your post.

    >>

    >> Which Eagle version are you using?

    >> Is your D2PAK a package you created or one from an Eagle library, so

    >> we can

    >> check how the package is constructed?

    >> i.e. Is the tab in the library package made from a single SMD pad or a

    >> polygon with or without a smaller SMD pad?

    >>

    >> While DRC is interpreted as Design Rule Check it does dynamically modify

    >> the board design, in real time.

    >>

    >> The image attached shows the two situations where the signal name and the

    >> polygon name are the same or different.

     

    I copied LM2937 from the linear.lbr into my own library. Since the tab

    did not have a pin connection on the schematic symbol, I added one. In

    the symbol, I named pin 1 GND@1 and for the tab I called it GND@2.

     

    The polygon has a name of GND, with isolate set to 0. I even tried

    setting the "same signal" clearances in DRC to 0. Nothing seems to work.

    It looks like the picture on the right that you sent with the little gap.

     

    Sorry, typing faster than I can think.  I named pin 2 (middle pin)

    GND@1, not pin 1.

     

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    On 2/29/2012 5:54 PM, Warren Brayshaw wrote:

    Your library is likely not created correctly or the gap you are seeing is a

    thermal gap.

    Attached is a modified library from Linear.lbr

    Image is from this library. Schematic and Board shown.

    As you can see it works.

     

    Warren

    Thanks Warren!

     

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    Your library is likely not created correctly or the gap you are seeing is a

    thermal gap.

    Attached is a modified library from Linear.lbr

    Image is from this library. Schematic and Board shown.

    As you can see it works.

     

    Warren

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

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  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    Your library is likely not created correctly or the gap you are seeing is a

    thermal gap.

    Attached is a modified library from Linear.lbr

    Image is from this library. Schematic and Board shown.

    As you can see it works.

     

    Warren

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

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Children
  • e14 Contributor
    e14 Contributor over 14 years ago in reply to e14 Contributor

    On 2/29/2012 5:54 PM, Warren Brayshaw wrote:

    Your library is likely not created correctly or the gap you are seeing is a

    thermal gap.

    Attached is a modified library from Linear.lbr

    Image is from this library. Schematic and Board shown.

    As you can see it works.

     

    Warren

    Thanks Warren!

     

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