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autoroute and vias and bga breakout

jkuzmack

Hello,

 

I am routing a large FPGA (1984 balls) to several RLDRAMs (168 balls each) and want to use the autorouter to simplify the effort in a 16 layer board.  Since there are mulitple differential clocks (routed manually) and data and address and other signals, I want to group the routes and apply them to particular layers.

 

So far, I've been partially successful.  I can apply signal groups to various layers but only if the bga ball has a via already routed to it (ie a breakout).  With no via, the autorouter will only route on layer 1. If I change layer 1 to N/A then I get the error message "Unreachable smd-pad in layer 1".  I am using a grid size of 0.1mm with parts on the grid and a routing grid of 0.1mm.  I've also tried finer resolution for both with no difference in results.  I've also set the cost of layer 1 to 10 (inner layers set to 1) but no change in results (only routes on layer 1).

 

Q1 What am I missing?  Is there some limitation with the autorouter inserting vias?

 

Given that vias must be present in order for the autorouter to apply routes to inner layers, I want to use a .ulp to automatically create the bga breakout.  I've tried "route-bga.ulp" but am not quite satisfied with the results. I don't want the 'hanging' traces, just the route from ball to via.  And I want a different breakout pattern, whereby the balls in the NW quadrant have breakout routes with a NW angle.  And likewise in the other quadrants.  This leaves a cross shaped channel in the middle of the part for additional bypassing.

 

Q2 Are there any other bga breakout ulp's available?  Has any modified "route-bga.ulp" for different breakout pattern and no inner layer routes?

 

Thanks for any help on this.

  • "John Kuzmack"  skrev i nyhetsmeldingen:

    301969897.01409166413080.JavaMail.jive@flmspu-csapp-02.premierfarnell.com

    ...

     

    I am routing a large FPGA (1984 balls) to several RLDRAMs (168 balls

    each) and want to use the autorouter to simplify the effort in a 16

    layer board.  Since there are mulitple differential clocks (routed

    manually) and data and address and other signals, I want to group the

    routes and apply them to particular layers.

     

    Whoaa! I wouldnt even dare to go there.

    If the autorouter is capable of doing the length match and the pin swapping

    needed to meet the FPGA placement rules, the autorouter is much better than

    I thought.

     

    I recently did a 10 layer design with two high speed 36bit RLDRAM's and I

    routed one manually and copied the routing to the other, exploiting bank

    symmetry (I had to put one ram on the other side), and did some adjustment

    to meet the fpga pins. I hope you will get away with less than 36bit, cause

    that design was pretty congested around the ram's. But it worked image

    I also did a 16 layer board with 4 240pin dimms and two 1152 pin fpga's some

    time ago, and even there I could use fpga bank symmetry to save time.

     

    Unless you run it on slow IO, you have a tough job there!

     

     

     

     

  • in reply to autodeskguest

    As I understand it, the length matching would have to be done manually or semi-manually (using meander) depending upon trace spacing and length disparity and how the signal groups are applied across layers.  I am assuming that there is no length criteria associated with the autorouter although I haven't gone through all the cost variables in detail yet.

     

    I will look into whether bank symmetry can apply in my case.  Thanks.

  • in reply to jkuzmack

    "John Kuzmack"  skrev i nyhetsmeldingen:

    1094359778.41409245926301.JavaMail.jive@flcspu-csapp-01.premierfarnell.com

    ...

     

    As I understand it, the length matching would have to be done manually

    or semi-manually (using meander) depending upon trace spacing and length

    disparity and how the signal groups are applied across layers.  I am

    assuming that there is no length criteria associated with the autorouter

    although I haven't gone through all the cost variables in detail yet.

    I will look into whether bank symmetry can apply in my case.  Thanks.

     

    I ended up with so dense wiring, that I even had to do the meanders

    manually. It ended up not like traditional meanders (they consume alot of

    space), but rather routing around the bush abit. I used ~0.1mm width, and

    did most of the routing on 4 layers. The others are power and reference

    planes. Since you got more layers, you may have a better starting point.

     

    Here is how it looks http://postimg.org/image/kavk6os9d/full/

     

    Let me know if you get a good result with the autorouter image