via diameter

I'm not sure that this would not create some trouble for the PCB manufacturer, for the plating process. Even if the holes are plated after the assembly of all layers, I think it would help to have some copper.

Maybe you could use blind/buried via instead (you have to change the Layer configuration). The result would be better, since you would have no drill at all on some layers. But the manufacturing process is a little bit expensive, because some holes have to be plated, before the complete layers assembly.

An other solution is the micro-via, (they are blind too), but smaller.

Guillaume.

Removing rings from outer layers maybe is a problem during plating process,

but I am thinking about inner layers.

From my experience when I sending gerber files to manufacture, in most

cases they remove unconnected VIAs ring on inner layers

For example we have 4 layer board, signals are only on top and bottom.

Inner layers are for power and ground polygons, so every signals vias make

hole in polygon on inner layers. If we remove vias ring on inner layer then

the hole in polygon will be smaller, and that what I need.

Micro vias and blind vias are not solution here.

PGW

Hi,

You're right, for 4 layer board, with GND and power on inner layer, blind via and micro via doesn't help.

But in my experience Manufacturer doesn't always remove the ring of inner layer. Maybe it's depend on their process and on the size of the ring. And maybe it could be a problem of a too small ring size, If the ring is not large enough, manufacturer can have some trouble, and in that case it's better to have no ring at all ? this could be why he remove the rings ?!? (if you know why they remove your rings, I would be glad if you could tell me, because I'm curious about it ...)

Anyway, if you use the 2 inner layers only for GND and VCC planes, you can reduce the inner layer in the resting parameters. Since the connected via will be connected to a plane, there is no 'ring' (or I can say a giga big ring called Polygon !)

It's true that your suggestion could help to have a better control and better plane. But still, you will have a hole in the plane (drill + isolation + a little margin to compensate the misalignment between layers and drills ). And sometime, we had to accept that 4 layers is just enough to connect everything, but it's not good enough to do a good design !

Ok Ok, You will say 'more 4 layers is cheaper' or 'sometimes additional layer doesn't help' ... and you will be right to !

Guillaume.

Hi

Of course I will still have holes in polygons, but look how is the

difference:

http://imagizer.imageshack.us/a/img540/3247/UphPKP.jpg

http://imagizer.imageshack.us/a/img909/6360/QR1aN8.jpg

Now I use workaround, that mean I set vias diameter to auto and in restring

parameteres I set vias diameter on inner layers to 0. But I can do that

only if via has no trace on inner layer and I have to set manually for some

vias diameter to auto for rest to specific value.

That improvement will save me some work.

Now I think that if we remove inner rings from via, it will be look like in

2 layers board. Probably manufacturer should have no problem with plating.

I never asked them why they remove unconnected rings.

PGW

Hi,

I'm glad you found a workaround.

And, yes, it could be a great idea to add an option on via, to automatically remove unnecessary ring.

But, I would add that this option could also be useful on through hole pads... I've just finish a power board, and on connector, it would be useful to reduce or remove ring on inner layer (but in my case it was for a better isolation).

Guillaume.