Details about how tPlace layer needs to be managed?

On 17/10/15 12:28, David Alenhag wrote:

Hello.

 

Some time ago I read or heard(in a youtube video) that I can use the

tPlace layer when drawing the outlines for packages and such and I don't

need to avoid drawing over pads since some other layer exists that cover

all pads and that this layer will not allow anything to be printed on

top of it when the board is manufacturerd.

But then other sources tells me that I MUST not use tplace layer

drawings that cover any part of any pad and so I have to draw any figure

with two layers tPlace and tDocu so that it looks almost as a complete

drawing but all lines that cover pads would be made in tDocu.

 

I am in the process of designing my very first board to be sent of China

to be printed for real and I don't jet know enough about gerber file to

be able to find this out.

 

Do anyone know?

Am I making a big mistake when only using tPlace and draw lines over

pads?

 

OK, well, it's not as clear-cut as that. In fact, the layers don't

matter, it's what goes in the Gerber that matters, but since that's

usually tPlace+tNames for the silk screen let's deal with those two.

In principle, the tPlace and tNames will become ink, which is not

solderable and therefore must be kept away from any pads. Certainly,

when designing library parts, this is the rule you should follow, and

use tDocu for the bits you want on the parts placement diagram but not

the silk screen.

In reality, when you actually use a component on a real circuit board

design, there's a very high probability you'll want to put a via right

slap bang on the outline, or a pad of another device under the pin one

marker. That would cause just as much trouble as errors in the library,

when it comes to production.

Also, there's a solder mask between the copper and the ink, which is not

solderable either (obviously; it's what it's there for). That is

controlled by the tStop layer.

So, what the majority of board fabrication houses do is to take your

solder mask Gerber (the tStop layer) and use it as a mask for the silk

screen Gerber also. This means that any undesirable bits of outline get

removed.

What it also means, of course, is that anything from tNames (important

component identification text) that gets too close to a via will be

removed. So you need to "smash" all your parts and move the identifiers

to somewhere clear of such interference, but still associated with the part.

It should also be noted that I'm talking about good quality European

board houses here. It may be that the cheap Chinese ones don't take this

extra care and will blithely print silk screen all over your pads if you

don't take the trouble to do it right yourself.