Hello,
I have a question about setting the board edge copper offset. I am sure I am doing something wrong on my side, I would guess I have set something that is overriding the COPPER/DIMENSION setting under the DISTANCE tab in DRC.
Currently the copper offset on the board is 10 mil. No matter what I set the COPPER/DIMENSION setting to (15 mil, 20 mil, 50 mil, etc.) the copper polygon offset from the board edge stays at 10 mil.
I have three separate copper "fill" polygons on my power plane (VDDD, VDDA, +12V). All three of them touch the board edge on at least one side. Perhaps having three different fill polygons is causing the problem? The internal spacing between the different power plains is 8 mil. So the interior spacing is different than the edge spacing, but again, I can not seem to change to edge spacing no matter what I set the COPPER/DIMENSION setting under the DISTANCE tab to.
The ISOLATE property of each copper pour is "0" (Use DRC value).
I have the same issue on the internal ground plain (VSSD, VSSA, GND) and the top and bottom plains. I can solve the issue on the top and bottom using the tRestrict and bRestrict layers, but this does not help me on the internal POWER and GROUND plains.
Any suggestions would be most appreciated.
Thanks,
Dave
