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Why does Eagle not have a "standard" way to link Analogue and Digital grounds

Former Member

The common practice is to keep the analogue and digital grounds seperate and then link them at 1 point. Many  people that have tried to do this over the years have used various work arounds to do this in a "safe" manner without getting DRC errors. Other people have done things that generated DRC errors and then approved them like create a part that has overlapping pads. In either case, the search gives the impression that the Eagle PCB does not have a standard built in method to allow this. Why?

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    Possibly because there are many ways to do it which for most people are good enough. Approving one DRC error isn't the end of the world. If I have separate grounds I usually create the star point for AGND and 0VD connections with a resistor jumper so I can easily disconnect during debug or fit other components if there are issues. However, with good design practices, partitioning grounds often isn't necessary and can lead to it's own signal integrity issues for any signals having to cross the boundary between the separate grounds.

     

    Mentor Graphics in their DxDesigner have a horrible way using net aliases to alias one global net to another. Until a couple of years ago this totally broke when you had a design with hierarchy, so basically for anything but small designs it was broken. I don't know what Cadence or Altium do for this. If you have suggestions for how this could work then maybe pop it into the suggestions forum.

     

    Best Regards,

     

    Rachael

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  • 0

    Possibly because there are many ways to do it which for most people are good enough. Approving one DRC error isn't the end of the world. If I have separate grounds I usually create the star point for AGND and 0VD connections with a resistor jumper so I can easily disconnect during debug or fit other components if there are issues. However, with good design practices, partitioning grounds often isn't necessary and can lead to it's own signal integrity issues for any signals having to cross the boundary between the separate grounds.

     

    Mentor Graphics in their DxDesigner have a horrible way using net aliases to alias one global net to another. Until a couple of years ago this totally broke when you had a design with hierarchy, so basically for anything but small designs it was broken. I don't know what Cadence or Altium do for this. If you have suggestions for how this could work then maybe pop it into the suggestions forum.

     

    Best Regards,

     

    Rachael

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