How to add graphics or text in copper without errors?

On 17/01/18 11:29, James Richters wrote:

Is there any way to draw traces without pads?

Not "traces" but you can draw on the copper layers with the "wire"

(line) tool, or the arc tool, or others. I think some of those do get a

net name created for the segments, which isn't usually a problem.

 

I can add Text and define it to be on the bottom layer so it would be in copper, but I get an error in DRC for 'Width'  which I don't understand because the lettering looks good to me. it even automatically makes it backwards when I select the bottom layer, but I still get the DRC error.  What's the best way to define this?

The DRC error is because the text, when rendered, results in traces of

copper that are narrower than your DRC rules allow. You can fatten up

the text or just ignore the DRC error.

 

I have managed to force traces by importing a DXF file to the bottom layer, but when I run DRC I get a whole list of overlap and clearance issues with the imported copper traces,

The DXF import probably creates a lot of separate lines, each of which

gets its own net, so where they overlap it's an error.

is there a way to define these as graphics in copper or something so the DRC ignores it? Is there some way to combine the separate lines and arcs that got imported from the DXF file into a continuous trace so they don't show up as overlaps?  When I import the same DXF file to the silk screen layer, it doesn't get any DRC errors.

There's no overlap checking on the silk layer because the silk layer

doesn't create electrical connections.

 

Is there a way to automatically make holes in the solder mask only around the graphics traces, or text so the graphics or text end up coated with solder?  

You can copy the text/graphics into the mask layer but it's not a single

step. What you do is group them all, "CUT" (the scissors icon, which

actually copies) then PASTE somewhere off-board. Now group the copies,

do CHANGE LAYER to put them on tMask/bMask, then MOVE the group back to

overlap the originals.

 

Should I be putting things I just want to leave in copper on the bottom on some other layer besides bottom that will do what I want it to?

That depends how you plan to produce the board. It's perfectly possible

to do what you want by creating a new custom layer for all this stuff,

then arranging for that layer to be present in the Gerber (or printout,

if home etching) for the copper layer.

 

Any help is greatly appreciated

 

Thank you very much for the information!

I have got almost everything working now except for the issue with DXF Import:

The DXF import probably creates a lot of separate lines, each of which

gets its own net, so where they overlap it's an error.

Yes, this seems to be the case, some sections of the imported DXF file have different signal names.  I suspect it has to do with the order the entities are saved in the DXF file, as it's only a few sections of my import that have this issue.   Is there a way to force all the signal names of a group to a specific value?   I thought I could perhaps group all connected segments together and use the change feature to change all the signal names, but I don't see a way to change that particular field.  any thoughts on how to change or merge or connect the segments so they are part of the same net?

The DRC error is because the text, when rendered, results in traces of

copper that are narrower than your DRC rules allow. You can fatten up

the text or just ignore the DRC error.

I was able to get rid of the width error by fattening up the text a little.  But now I notice if I use the proportional font, I get an error for No Vector Font if it's on the bottom copper layer.  I like the lettering of the proportional font better, is there a way to get it to accept this or can the error just be ignored / approved? 

On 17/01/18 19:58, James Richters wrote:

Thank you very much for the information!

I have got almost everything working now except for the issue with DXF Import:

The DXF import probably creates a lot of separate lines, each of which

gets its own net, so where they overlap it's an error.

Yes, this seems to be the case, some sections of the imported DXF file have different signal names.  I suspect it has to do with the order the entities are saved in the DXF file, as it's only a few sections of my import that have this issue.   Is there a way to force all the signal names of a group to a specific value?   I thought I could perhaps group all connected segments together and use the change feature to change all the signal names, but I don't see a way to change that particular field.  any thoughts on how to change or merge or connect the segments so they are part of the same net?

I don't think you can rename a group but you can rename individual

traces with the "NAME" tool. If you name them all the same, Eagle will

ask which name to merge the nets as but then it will expect the lines to

all be joined. Note that crossing each other does not count as joining.

You will get airwires between the various lines.

It's possible to fix all the errors by laboriously tweaking each line to

satisfy the rules. It's probably better (certainly easier) either to

just "approve" all the errors or tackle the problem another way (such as

the custom layer method I briefly mentioned before).

I don't think you can rename a group but you can rename individual

traces with the "NAME" tool.

Thank you again, the "Name" tool did the trick, I only needed to change the name of one segment to match and it merged the two groups together.

I found an option in the DRC under MISC for Font,  if I take the checkmark out of it, I no longer get errors for using the proportional font on my bottom copper layer.   I'm curious though why they even have the option for the check?  is there some problem using the proportional font on the copper layer?   I'm planning on having the boards produced professionally, and I want to make sure they come out correctly.

I found an option in the DRC under MISC for Font,  if I take the checkmark out of it, I no longer get errors for using the proportional font on my bottom copper layer.   I'm curious though why they even have the option for the check?  is there some problem using the proportional font on the copper layer?   I'm planning on having the boards produced professionally, and I want to make sure they come out correctly.

On 18/01/18 20:35, James Richters wrote:

I found an option in the DRC under MISC for Font,  if I take the checkmark out of it, I no longer get errors for using the proportional font on my bottom copper layer.   I'm curious though why they even have the option for the check?  is there some problem using the proportional font on the copper layer?   I'm planning on having the boards produced professionally, and I want to make sure they come out correctly.

 

If you get your boards made professionally, you will be generating

Gerber files. These are a vector graphic format. The proportional fonts

cannot be represented in Gerber so Eagle will be forced to use the

vector fonts.

So yes, there is a problem using the proportional font on any layer that

you want to include in the final board. Your board house will be etching

the copper to match the vector font and this will result in copper

traces of the width this produces. The board house will have minimum

copper widths they are confident of accurately producing and thus, if

you actually care about the text being correctly reproduced, you do need

to check it doesn't violate that width limit.

Thank you for the explanation, I'm glad I asked or I would probably not get the result I was after.  I noticed when I change from proportional to vector font, it can affect how wide the entire line is.  I decided to generate a stick font in my cad program and export a DXF file, then import it into Eagle and specify an acceptable line width.  I also found out that if I have something I want filled that as long as I actually connect the individual hatch lines to each other, it solves the issue of having overlap error.