Clearance error even though DRC is fine!

Am 03.03.2019 um 21:50 schrieb Jan-Jelle Huizinga:

Good evening,

 

I am breaking my head on a clearance error in Eagle.

 

The W5500 gives me clearance errors between all pads, while the distance between the pads is well within the allowed pad-distance of the DRC. distance between pads is 7.9mm.

 

I tried all settings but it seems like this problem is within the component itself. any suggestions what I could do about it?

 

Much appreciated!

 

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I'm breaking my head about what you mean.

First of all you should tell the eagle version you use.

Second would it be very nice if you provide a link to the device you

talking about so that users wanting to help you know what we are talking

about.

Third would it be very helpful to add the eagle files here or at least

place a picture.

A pad distance of 7,9mm????

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Mit freundlichen Grüßen / With best regards

Joern Paschedag

Hi,

Thanks for the reply. Fair enough hehe, I put a bit more detail in below. I made the request in a bit of a hurry hoping someone would tell me something obvious I missed.

The eagle version I am using is: 8.4.1

The chip in question is the Wiznet W5500. see link: https://www.wiznet.io/product-item/w5500/

The problem in eagle board layout is:

The clearance error.

The pad distance was 7.9 mil, not mm. apologies for the typo.

I can add the board file is that is required. the problem is that I've changed the DRC file for the SMD pad distance but the error remains. see picture:

And even the default value of 6 mil should be fine. however, the clearance error doesn't disappear.

Could you point me in any direction?

Much appreciated!

You can use the footprint SQFP-S-7X7-48.fpt in the smd-ipc.lbr

(this name is with Eagle Version 9.3.1; you have a similar extension of the parts name).

Just copy it into your created device and connect it with their pin numbers.

Remember: check every time if you need the mm or inch or mil grid.

This part is drawn in mm.

So you have to set in the library 'footprints' the grid in 0.25mm for placing the pins or 0.125 mm for drawing more details.

Your drawings:

The pins are too wide and too long drawn.
The distance of 7.9 mm is unusual and irregular, a mistake.
Also note the Solder mask.

The observance of the grid is obligatory.

Regards

Gerald

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Hi Jan-Jelle,

have you checked your clearance settings in the net classes dialog?

HTH

Markus

Hi Markus,

No I havn't, what does this mean? I believe my experience with eagle is lacking here..

Thanks for the help!

Jan-Jelle

Am 05.03.2019 um 11:09 schrieb Jan-Jelle Huizinga:

No I havn't, what does this mean? I believe my experience with eagle is lacking here..

Short answer:

I think one of the involved net classes has a clearance setting higher

than 7.9 mil.

Long answer:

The effective value for clearance is the maximum of the two values

- clearance specified for the involved net classes (see HELP CLASS)

- clearance specified in the Design Rules

A good rule of thumb is:

Set the Design Rules to what you board house is able to do (for the

desired technology).

Set the net classes to what is necessary electrically (functionally and

according to safety regulations where applicable).

HTH

Markus

Ok Markus, you helped me out there.

I understand that copying parts of other schematics gives this kind of crap now, never realized the meta-data coming with the wires

I will have to do a full check on all the traces, and group them in the correct classes after setting the classes properly.

Thanks for helping me understand this feature in Eagle. I was not looking for a work-around by approving errors, but what was physically causing the error.

Much appreciated, it all works now!

Jan-Jelle

Really helpful for me too!

Really helpful for me too!