Hi to everyone,
recently I noticed an excessive dimension of the .brd file, a "ratsnest" time-to-execute too high (20 seconds or more) and a complete freeze of EAGLE when importing the file into a bigger schematic (and I need to import blocks for the job).
To give some numbers, in one case the schematic have less than 40 components, less than 20 net wires, and the .sch file is 350kB. This is acceptable.
Obviously the schematic and board are consistent, and there are no errors showed in DRC and ERC.
So, what is the problem? The problem is that the corresponding .brd file is over 12MB and it contains about 350'000 rows of "signal" which are NOT used by the schematic, therefore every operation in the board editor takes a looong time with respect to "normal" files!
There is a way to clear "unused" signals from the .brd file without loss the consistence with schematic?
Many of it are power signals...for example I see thousands of VDD, like "VDD1, VDD2, VDD3...VDD19561" and so on, when in the schematic there is no VDD nets or signal...nothing named "VDD".
The ULPs I found do not rename signals neither it delete unused elements. Nothing of useful on my desk.
The older files works fine with the same software, even if there are hundreds of components and nets, no problems of speed or funcionality or importing.
The problem seems to be in that files full of unused signals.
Despair is taking the place of hope: I have several .brd files with this problem, important projects fully routed, months of work...
Can someone help me? Thank you for the attention.