Wire list from board

Hi Greg,

    Thanks for bringing that to my attention.

I assumed you had gone through a full creation of the BRD, from an SCH.

   Still,  I wonder if creating a board directly, naming signals, and

running a ratsnest, might still create a normal Eagle netlist file, ( which

would still make the wirelist ulp work).

Then again, perhaps the standard Eagle Netlist is all you need, if that

would happen.

Check what production files Eagle created for you, when creating just a BRD

file (with your named signals).

Good luck,

Joe

"gregrycm" <gregrycm@insightbb.com> wrote in message

news:fviajg$6df$1@cheetah.cadsoft.de...

Thanks for the suggestion.

I downloaded the UPL and ran on the board and got the following output:

 

1. EAGLE Version 4.16r2 Copyright (c) 1988-2006 CadSoft

 

1. WW_TESTPNTS.ULP Version 1.0  - Wire Wrapping Board Netlist / SCR Script

File, generator

 

1. C:/PWB Layout/Eagle-4.16r2/projects/Design1/8051-3PORT.brd

2. on  5/03/2008 01:15:20p

 

1. WIRE WRAP Netlist with Wire Wrap Board pin

locations.

1. A FLAG (*) after Pin-X or before Pin-Y, means the PART's pad is not

placed exactly on

1. a standard 0.1 inch (2.54 mm) EAGLE BOARD grid line (Check: X & Y mils

coordinates)

1. This may be O.K. (e.g. thin board edge) - Pin Position is ROUNDED UP to

CORRECT spacing.

 

1. Net      Part       Pad  Pin-X ,  Pin-Y      X mils       Y mils   Wire

Length mils

 

Same results as running the EXPORT NETLIST.  I think what has happened

here is that the board was created without a schematic.  Parts were simply

placed and connected with traces.... without a ratsnest.  The board is not

too complicated, so I should be able to trace the board out and then

create a schematic, then create a new board with the necessary revisions.

 

Thanks for your help.

Greg

 

 

 

"Joseph Zeglinski" <J.Zeglinski@rogers.com> wrote in message

news:fvi9h2$3ua$1@cheetah.cadsoft.de...

Hi,

 

   I wrote a "WIRELIST.ulp" and submitted it to the Eagle ULP library

(see near the end of the ulp list).

It does exactly what you need, and a bit more.

 

   I needed a BRD file,  "post processor",  after an Eagle board is

populated, to create an "optimized wire length point to point wire wrap

list" - so I could test a project using a prototype project board, before

committing to a PCB.

The wire lengths are scanned and optimized. The resulting TXT file

contains NET names (based on the signal name), the name of the component,

the pad/pin number and its XY board coordinate, and point to point length

of wire.

   You can even graphically display the wrapped wire runs on the BRD,

just like a routed PCB air wire display.

 

The TXT file header will also contain the "date and time of the run",

just to keep track of and distinguish parts placement changes, that occur

during iterations of the project during development.

 

   There is an extensive description and user guide in the ULP comments

header.

Since I wrote it in an intensive session over two years ago, for Eagle

rev 4.15, I really don't recall all the details, but it is fully

debugged, and fully documented.

 

Hope this helps.

Joe

 

   Here is a "sample output" section  (ALTAZ-JAZ-24C.txt),  of one of my

normal Eagle  BRD projects:

If one would wire the project in this exact sequence, it would use the

least amount of wire, and therefore shortest point-to-point signal run.

 

*************************************************************

EAGLE Version 4.15 Copyright (c) 1988-2005 CadSoft

 

J.A.Z. - Netlist with pin locations

exported from C:/Documents and Settings/Joe/My Documents/EAGLE

PROJECTS/DUAL AXIS/ALTAZ-JAZ-24C.brd at 01/09/2005 02:01:01a

 

Net        Part     Pad              x                         y Wire

Length (mil)

 

+POS     R12        1      3750.000000     3950.000000       0.000000

              J9J1       1      3951.000000     3950.000000

201.000000

 

-NEG     NN3       3     4050.000000     3600.000000       0.000000

             J9J1        2      4149.000000     3950.000000

363.732044

 

0.5X     JP6         8       4050.000000      1950.000000       0.000000

            IC19       1      4650.000000      1050.000000    1081.665383

            IC19       2      4750.000000      1050.000000     100.000000

            IC27      12     5650.000000      1550.000000    1029.563014

            IC27       8      6050.000000      1550.000000     400.000000

 

1.5X     JP6         6      3950.000000      1950.000000       0.000000

            IC30       5      4150.000000      2050.000000     223.606798

            IC19      13     4950.000000      1350.000000    1063.014581

            IC19      12     5050.000000     1350.000000     100.000000

***************************************************************************

 

"gregrycm" <gregrycm@insightbb.com> wrote in message

news:fvgmr6$2h0$1@cheetah.cadsoft.de...

Hello,

 

I have a board layout, and want to create a ASCII file that lists all

the net names and components that make up each net.

 

I have tried to Export a Netlist from the board, but only get the

following:

 

Netlist

Exported from 8051-3PORT.brd at  5/02/2008 10:21:39p

EAGLE Version 4.16r2 Copyright (c) 1988-2006 CadSoft

Net      Part     Pad

 

 

 

Thanks,

Greg

 

Hi Greg,

    Thanks for bringing that to my attention.

I assumed you had gone through a full creation of the BRD, from an SCH.

   Still,  I wonder if creating a board directly, naming signals, and

running a ratsnest, might still create a normal Eagle netlist file, ( which

would still make the wirelist ulp work).

Then again, perhaps the standard Eagle Netlist is all you need, if that

would happen.

Check what production files Eagle created for you, when creating just a BRD

file (with your named signals).

Good luck,

Joe

"gregrycm" <gregrycm@insightbb.com> wrote in message

news:fviajg$6df$1@cheetah.cadsoft.de...

Thanks for the suggestion.

I downloaded the UPL and ran on the board and got the following output:

 

1. EAGLE Version 4.16r2 Copyright (c) 1988-2006 CadSoft

 

1. WW_TESTPNTS.ULP Version 1.0  - Wire Wrapping Board Netlist / SCR Script

File, generator

 

1. C:/PWB Layout/Eagle-4.16r2/projects/Design1/8051-3PORT.brd

2. on  5/03/2008 01:15:20p

 

1. WIRE WRAP Netlist with Wire Wrap Board pin

locations.

1. A FLAG (*) after Pin-X or before Pin-Y, means the PART's pad is not

placed exactly on

1. a standard 0.1 inch (2.54 mm) EAGLE BOARD grid line (Check: X & Y mils

coordinates)

1. This may be O.K. (e.g. thin board edge) - Pin Position is ROUNDED UP to

CORRECT spacing.

 

1. Net      Part       Pad  Pin-X ,  Pin-Y      X mils       Y mils   Wire

Length mils

 

Same results as running the EXPORT NETLIST.  I think what has happened

here is that the board was created without a schematic.  Parts were simply

placed and connected with traces.... without a ratsnest.  The board is not

too complicated, so I should be able to trace the board out and then

create a schematic, then create a new board with the necessary revisions.

 

Thanks for your help.

Greg

 

 

 

"Joseph Zeglinski" <J.Zeglinski@rogers.com> wrote in message

news:fvi9h2$3ua$1@cheetah.cadsoft.de...

Hi,

 

   I wrote a "WIRELIST.ulp" and submitted it to the Eagle ULP library

(see near the end of the ulp list).

It does exactly what you need, and a bit more.

 

   I needed a BRD file,  "post processor",  after an Eagle board is

populated, to create an "optimized wire length point to point wire wrap

list" - so I could test a project using a prototype project board, before

committing to a PCB.

The wire lengths are scanned and optimized. The resulting TXT file

contains NET names (based on the signal name), the name of the component,

the pad/pin number and its XY board coordinate, and point to point length

of wire.

   You can even graphically display the wrapped wire runs on the BRD,

just like a routed PCB air wire display.

 

The TXT file header will also contain the "date and time of the run",

just to keep track of and distinguish parts placement changes, that occur

during iterations of the project during development.

 

   There is an extensive description and user guide in the ULP comments

header.

Since I wrote it in an intensive session over two years ago, for Eagle

rev 4.15, I really don't recall all the details, but it is fully

debugged, and fully documented.

 

Hope this helps.

Joe

 

   Here is a "sample output" section  (ALTAZ-JAZ-24C.txt),  of one of my

normal Eagle  BRD projects:

If one would wire the project in this exact sequence, it would use the

least amount of wire, and therefore shortest point-to-point signal run.

 

*************************************************************

EAGLE Version 4.15 Copyright (c) 1988-2005 CadSoft

 

J.A.Z. - Netlist with pin locations

exported from C:/Documents and Settings/Joe/My Documents/EAGLE

PROJECTS/DUAL AXIS/ALTAZ-JAZ-24C.brd at 01/09/2005 02:01:01a

 

Net        Part     Pad              x                         y Wire

Length (mil)

 

+POS     R12        1      3750.000000     3950.000000       0.000000

              J9J1       1      3951.000000     3950.000000

201.000000

 

-NEG     NN3       3     4050.000000     3600.000000       0.000000

             J9J1        2      4149.000000     3950.000000

363.732044

 

0.5X     JP6         8       4050.000000      1950.000000       0.000000

            IC19       1      4650.000000      1050.000000    1081.665383

            IC19       2      4750.000000      1050.000000     100.000000

            IC27      12     5650.000000      1550.000000    1029.563014

            IC27       8      6050.000000      1550.000000     400.000000

 

1.5X     JP6         6      3950.000000      1950.000000       0.000000

            IC30       5      4150.000000      2050.000000     223.606798

            IC19      13     4950.000000      1350.000000    1063.014581

            IC19      12     5050.000000     1350.000000     100.000000

***************************************************************************

 

"gregrycm" <gregrycm@insightbb.com> wrote in message

news:fvgmr6$2h0$1@cheetah.cadsoft.de...

Hello,

 

I have a board layout, and want to create a ASCII file that lists all

the net names and components that make up each net.

 

I have tried to Export a Netlist from the board, but only get the

following:

 

Netlist

Exported from 8051-3PORT.brd at  5/02/2008 10:21:39p

EAGLE Version 4.16r2 Copyright (c) 1988-2006 CadSoft

Net      Part     Pad

 

 

 

Thanks,

Greg