net signal name inconsistency error report despite consistent layout & schematic

Pankaj Kataria schrieb:

Hello

 

I am new to Eagle and I am using EAGLE Version 4.15 Copyright (c) 1988-2005

CadSoft

 

I am getting 3 errors/warnings about net name inconsistency in-between the

schematic and layout (pcb). Except for  one of the errors/warnings, I do not

see anything wrong when I use show "net name" in both schematic and PCB.

 

Here is an excerpt of what I get with erc.

 

"..............

 

Pins/Pads with different connections:

 

  Part                        Gate     Pin        Net

Pad      Signal

 

  SV1                       G$1      13         BYPASS_ON           13

S$5

VCO_CHOKE       G$1      P$2        VDD               P$2

X_VCO_SUPPLY    G$1      1          DC_PROBE_OUT      1

 

ERROR: Board and schematic are not consistent!

 

    1 errors

   21 warnings

 

.............."

 

 

 

1. First of all it seems like I have 3 errors but the erc report says there

is only 1 error. Which one of the three is really an error?

ERC first checks the schematic for plausibility and additionlly

compares schematic and board, if existing.

All messages are classified as a warning or an error. Read the messges

and decide what to do.

The messages concerning consistency are at the end of the ERC file.

In your case all those about different connections in sch/brd.

2. Upon investigation of the first warning/error, in the PCB I am seeing the

net/signal S$5 as a dot on the pin of SV1 device (MA13-2- "PIN HEADER")

device. However in the PCB I have this pin connected correctly to the signal

"BYPASS_ON" just like the schematic. I just can't get rid of this "S$5". I

tried ripup but S$5 stays. I moved the device to see if any net (in the form

of a dot) stays behind but none does. It is almost like somehow S$5 is

embedded onto this pin #13. By the way there is no net S$5 in the schematic

anywhere.

 

Any advice?

Try to set a VIA with name S$5 near the pad. RATSNEST should calculate

an airwire now. Can you delete S$5 now?

 

3. As far as the last two warnings/errors are concerned. I feel I have

correctly connected the pins of these devices in the PCB layout and given

the nets correct name using name command. My interpretation of the last two

warnings are that in the layout the pins of the parts are not connected to

any signal. I do not understand why these two warnings are appearing. Any

suggestions?

 

The pad in the layout are not connected to any signal. So you have to

draw an airwire (SIGNAL command) and name it the same as it is in

the schematic. Aferwards start ERC. Schematic and board should be

consistent again.

How comes difference? Maybe you accidentally closed the board file

and connected the pins in the schematic....

--

Mit freundlichen Gruessen / Best regards

Richard Hammerl

  CadSoft Support -- hotline@cadsoft.de

  FAQ: http://www.cadsoft.de/faq.htm

Pankaj Kataria schrieb:

Hello

 

I am new to Eagle and I am using EAGLE Version 4.15 Copyright (c) 1988-2005

CadSoft

 

I am getting 3 errors/warnings about net name inconsistency in-between the

schematic and layout (pcb). Except for  one of the errors/warnings, I do not

see anything wrong when I use show "net name" in both schematic and PCB.

 

Here is an excerpt of what I get with erc.

 

"..............

 

Pins/Pads with different connections:

 

  Part                        Gate     Pin        Net

Pad      Signal

 

  SV1                       G$1      13         BYPASS_ON           13

S$5

VCO_CHOKE       G$1      P$2        VDD               P$2

X_VCO_SUPPLY    G$1      1          DC_PROBE_OUT      1

 

ERROR: Board and schematic are not consistent!

 

    1 errors

   21 warnings

 

.............."

 

 

 

1. First of all it seems like I have 3 errors but the erc report says there

is only 1 error. Which one of the three is really an error?

ERC first checks the schematic for plausibility and additionlly

compares schematic and board, if existing.

All messages are classified as a warning or an error. Read the messges

and decide what to do.

The messages concerning consistency are at the end of the ERC file.

In your case all those about different connections in sch/brd.

2. Upon investigation of the first warning/error, in the PCB I am seeing the

net/signal S$5 as a dot on the pin of SV1 device (MA13-2- "PIN HEADER")

device. However in the PCB I have this pin connected correctly to the signal

"BYPASS_ON" just like the schematic. I just can't get rid of this "S$5". I

tried ripup but S$5 stays. I moved the device to see if any net (in the form

of a dot) stays behind but none does. It is almost like somehow S$5 is

embedded onto this pin #13. By the way there is no net S$5 in the schematic

anywhere.

 

Any advice?

Try to set a VIA with name S$5 near the pad. RATSNEST should calculate

an airwire now. Can you delete S$5 now?

 

3. As far as the last two warnings/errors are concerned. I feel I have

correctly connected the pins of these devices in the PCB layout and given

the nets correct name using name command. My interpretation of the last two

warnings are that in the layout the pins of the parts are not connected to

any signal. I do not understand why these two warnings are appearing. Any

suggestions?

 

The pad in the layout are not connected to any signal. So you have to

draw an airwire (SIGNAL command) and name it the same as it is in

the schematic. Aferwards start ERC. Schematic and board should be

consistent again.

How comes difference? Maybe you accidentally closed the board file

and connected the pins in the schematic....

--

Mit freundlichen Gruessen / Best regards

Richard Hammerl

  CadSoft Support -- hotline@cadsoft.de

  FAQ: http://www.cadsoft.de/faq.htm