My board fab house (Advanced Circuits in USA) has a requirement that copper regions must be spaced apart by at least 5 mils, even when the copper sections are of the same signal. Eagle's polygon pour (fill) seems to violate this requirement regardless of the Width of the polygon used for filling. The problem appears identically in screen images of the fill and in Gerbers filled using gerb274x-4layer.cam. In the example attached, design rules were set for all clearances between signals (the same or different) to be 6 mils and the polygon width is also 6 mils.
As you can see in the Eagle screen shot attached, at the center of the white circle, the fill has produced a gap of approximately 1 mil, apparently determined by the via-via spacing geometry. Unfortunately, although I have played with the Width parameter from 1 mil ~ 16 mils, there is no setting that will prevent the problem overall for the variety of via-via spacings that exist in my autorouted layout (6-mil grid). The problem appears to be unaffected by the Orphans and Isolate settings, except that of course some copper does not exist when Orphans is off.
I had this problem before with Eagle Version 5, and it is unchanged in the Eagle Pro Version 6.1.0 for Windows which I am using now.
Is there anything I can do to ameliorate this? It is very annoying, as my board house and I get into this circle of finger-pointing and fab delays.
Thanks so much. jb
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