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EAGLE User Support (English) My QFN Pad solution...
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Related

My QFN Pad solution...

Former Member
Former Member over 13 years ago

EAGLE 6.2.0, Windows 7.

 

Hi all.  Anyone see potiential problems with this work around to the vias in pad delima?  I have not had a board manufactured using this package yet but the Gerbers do look good and EAGLE does not generate any DRC errors.

 

Example library file included: QFN.zip

 

image

 

Steps used to create pad:

Assumes package centered on 0,0 coordinate with symetrically placed vias.

1.) Determine overall pad dimension for top layer.  In this example, it is 2.1mm square.

2.) Determine number of vias.  In this example, 4.

3.) Create 4 pads with the properties of square and the drill size preferred.  "Mirror", "Thermals", "Stop" and "First" properties Off (not checked).

    The "Stop" property could be left on.  I chose to turn it off and create the stops myself in each layer.

4.) Calculate the individual pad diameters (strange name for a square pad) for a 2x2 arrangement.

    This example:

          2.1mm (desired overall pad dimension) divided by 2 ( number of vias required in the X and Y axis) = 1.5mm

          Change Pad "Diameter" property to 1.5mm

5.) Calculate the positions of the 4 pads.

    This example:

          2.1mm (pad dimension) divided by 4 (number of vias in the X and Y axis times 2) = 0.525mm

          Change each pads "Position" property to the following:

              (-0.525, 0.525)     For the top left pad.

              (0.525, 0.525)     For the top right pad.

              (-0.525, -0.525)     For the bottom left pad.

               and

              (0.525, -0.525)     For the bottom right pad.

6.) Most of the time, these pads you just created will connect to another pad on the package.  So name the pads the same using the @ symbol.

    This example:

          Pin/Pad 12, which I have named VEE@12 (pin description and pin#)

          Change Pad 1 "Name" property to VEE@2.

          Change Pad 2 "Name" property to VEE@3.

          Change Pad 3 "Name" property to VEE@4.

          Change Pad 4 "Name" property to VEE@5.

 

I wanted the bottom layer pad to be a bit larger than the top so I added an SMD and assigned the following properties:

    Name: VEE@1

    Position: 0,0

    Angle: 0

    Mirror: Off (not checked)

    SMD Size: 2.5mm x 2.5mm

    Layer 16 Bottom

    Roundness: 0 %

    Thermals: Off (not checked)

    Stop: Off (not checked)

    Cream: Off (not checked)

 

7.)  In the Device, I made the following connections.  Note the multiple VEE's connected to G$1.VEE@12.

 

image

 

8.) On the board, I connected all of the VEE@ pads by routing traces as you would any airwire net.

 

I also created this QFN using the same methods:

 

image

 

Let me know what you think.

 

ADMsystems

Attachments:
QFN.zip
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  • Former Member
    0 Former Member over 13 years ago

    Alan Miller wrote:

    EAGLE 6.2.0, Windows 7.

     

    Hi all. Anyone see potiential problems with this work around to the

    vias in pad delima? I have not had a board manufactured using this

    package yet but the Gerbers do look good and EAGLE does not generate

    any DRC errors.

     

    Example library file included: QFN.zip

     

    Image:QFN16-4X4.bmp

     

    Steps used to create pad:

    Assumes package centered on 0,0 coordinate with symetrically placed

    vias.

    1.) Determine overall pad dimension for top layer. In this example,

    it is 2.1mm square.

    2.) Determine number of vias. In this example, 4.

    3.) Create 4 pads with the properties of square and the drill size

    preferred. "Mirror", "Thermals", "Stop" and "First" properties Off

    (not checked).

    The "Stop" property could be left on. I chose to turn it off and

    create the stops myself in each layer.

    4.) Calculate the pad diameters (strange name for a square pad). for

    a 2x2 arrangement.

    This example:

    2.1mm (pad dimension) divided by 2 ( number of vias required in the X

    axis) = 1.5mm

    Change Pad "Diameter" property to 1.5mm

    5.) Calculate the positions of the 4 pads.

    This example:

    2.1mm (pad dimension) divided by 4 (number of vias in the X axis

    times 2) = 0.525mm

    Change Pad "Position" property to:

    -0.525, 0.525 for the top left pad. Pad 1

    0.525, 0.525 for the top right pad. Pad 2

    -0.525, -0.525 for the bottom left pad. Pad 3 and

    0.525, -0.525 for the bottom right pad. Pad 4

    6.) Most of the time, these pads you just created will connect to

    another pad on the package. So name the pads the same using the @

    symbol.

    This example:

    Pin/Pad 12, which I have named VEE@12 (mailto:VEE@12) (pin

    description and pin#)

    Change Pad 1 "Name" property to VEE@2 (mailto:VEE@2).

    Change Pad 2 "Name" property to VEE@3 (mailto:VEE@3).

    Change Pad 3 "Name" property to VEE@4 (mailto:VEE@4).

    Change Pad 4 "Name" property to VEE@5 (mailto:VEE@5).

     

    I wanted the bottom layer pad to be a bit larger than the top so I

    added an SMD and assigned the following properties:

    Name: VEE@1 (mailto:VEE@1)

    Position: 0,0

    Angle: 0

    Mirror: Off (not checked)

    SMD Size: 2.5mm x 2.5mm

    Layer 16 Bottom

    Roundness: 0 %

    Thermals: Off (not checked)

    Stop: Off (not checked)

    Cream: Off (not checked)

     

    7.) In the Device, I made the following connections. Note the

    multiple VEE's connected to G$1.VEE@12 (mailto:G$1.VEE@12).

     

    Image:Untitled.bmp

     

    8.) On the board, I connected all of the VEE@ pads by routing traces

    as you would any airwire net.

     

    I also created this QFN using the same methods:

     

    Image:QFN32-7X7.bmp

     

    Let me know what you think.

     

    ADMsystems

     

     

     

    A couple of thoughts/precautions

     

    While your via holes are small in relation to the pad size you will not

    likely have an issue with the pad size changing due to the DRC settings but

    watch out with smaller areas as the DRC settings could increase the pad

    sizes.

     

    For the SMD on the bottom of the board you may find it more convenient to

    just place a polygon of copper there. I think v6 will let you do this so you

    wont have to address the addtional pad.

     

    Warren

     

     

    --

    Viewed / responded via the newsgroup at

    news.cadsoft.de

     

     

     

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    Good advice.  I hadnt thought about the DRC Restring settings.

     

    Alan

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