Power Planes (Polygon Tool Questions)

On 09/19/2012 10:36 PM, Jonathan Gordon wrote:

Hello, I have a question about using the polygon tool.

 

I just finished a design where I had half of my top layer as a VDD plane, and half of my top layer and a GND plane. On the VDD half of the board, I had a power plug and a voltage regulator with an associated capacitor. What I wanted to do was run a thick trace from the regulator to the capacitor and then have the VDD plane connected from the capacitor. This would make it so that everything connected to that plane would be "downstream" of the capacitor. However, because the trace to the capacitor and the plane had the same net (electrically they are connected) the plane simply overlapped the trace removing the "downstream" aspect. To solve the problem I had to make another polygon with a different net with a weird shape that followed the trace and gave it a higher rank so that the VDD plane couldn't get near the trace. Is there a more elegant way of solving this problem?

As for your wide trace to the first bypass capacitor, I have used

several methods:

• Change the shape of the polygon to exclude the area that will be

    occupied by the wide trace thus preventing the fill.

• Draw wires on the tRestrict or bRestrict layer (as appropriate) to

    box-out the area occupied by the wide trace.  The latter method will

    generate a DRC error where the trace overlaps the restrict wire, but

    these are easy enough to approve, then they won't bother you any more.

• Run the wide trace on a layer other than the filled layer and put a

    big fat juicy via at the end of it close to the capacitor(if it's

    SMD, or connect it directly to the capacitor's lead if it's PTH.

• The most elegant method is to create a "short" as a library device.

    This device has two pins in the symbol that adjoin each other, and

    overlapping SMD pads in the package.  This forms an electrical

    short, but keeps the nets logically separate.  In your schematic,

    place the short symbol in series between the regulator and the first

    cap in question.  On the board, place the short package close to the

    capacitor.  Now the wide trace maintains its identity as a net

    separate from VDD which causes the VDD polygon fill to pull back

    from it.  This has the advantage of not having to fiddle with the

    exact shape of the polygon or t/b Restrict wires should you move the

    wide trace.  You'll get DRC errors for overlapping SMD pads, which

    can be approved.

The method you used is perfectly valid since it gets the job done.

I have attached a shorts.lbr.  You can add packages with varying widths

of SMD pads as you feel appropriate, but it's a good example from which

to start.

I also had a similar problem where I wanted part of the plane to have islands and part of it to not have islands. In order to make some of the islands disappear I had to make extra polygons with different nets.

Lupo suggested creating multiple polygons for the same signal.  This is

a good way to achieve your goal in that you can control the

characteristics of each polygon separately.  i.e. You can turn Orphans

on for areas where you want islands, and off for areas where you don't

want islands.  But ALL the VDD polygons can have the same name.

I have also been know to place a wire in the tRestrict layer of as 1206

package to prevent copper fills underneath the part.  It's pretty easy

for a solder bridge to form under the part if you don't have a solder

mask (barebones board).

HTH,

    - Chuck

On 09/19/2012 10:36 PM, Jonathan Gordon wrote:

Hello, I have a question about using the polygon tool.

 

I just finished a design where I had half of my top layer as a VDD plane, and half of my top layer and a GND plane. On the VDD half of the board, I had a power plug and a voltage regulator with an associated capacitor. What I wanted to do was run a thick trace from the regulator to the capacitor and then have the VDD plane connected from the capacitor. This would make it so that everything connected to that plane would be "downstream" of the capacitor. However, because the trace to the capacitor and the plane had the same net (electrically they are connected) the plane simply overlapped the trace removing the "downstream" aspect. To solve the problem I had to make another polygon with a different net with a weird shape that followed the trace and gave it a higher rank so that the VDD plane couldn't get near the trace. Is there a more elegant way of solving this problem?

As for your wide trace to the first bypass capacitor, I have used

several methods:

• Change the shape of the polygon to exclude the area that will be

    occupied by the wide trace thus preventing the fill.

• Draw wires on the tRestrict or bRestrict layer (as appropriate) to

    box-out the area occupied by the wide trace.  The latter method will

    generate a DRC error where the trace overlaps the restrict wire, but

    these are easy enough to approve, then they won't bother you any more.

• Run the wide trace on a layer other than the filled layer and put a

    big fat juicy via at the end of it close to the capacitor(if it's

    SMD, or connect it directly to the capacitor's lead if it's PTH.

• The most elegant method is to create a "short" as a library device.

    This device has two pins in the symbol that adjoin each other, and

    overlapping SMD pads in the package.  This forms an electrical

    short, but keeps the nets logically separate.  In your schematic,

    place the short symbol in series between the regulator and the first

    cap in question.  On the board, place the short package close to the

    capacitor.  Now the wide trace maintains its identity as a net

    separate from VDD which causes the VDD polygon fill to pull back

    from it.  This has the advantage of not having to fiddle with the

    exact shape of the polygon or t/b Restrict wires should you move the

    wide trace.  You'll get DRC errors for overlapping SMD pads, which

    can be approved.

The method you used is perfectly valid since it gets the job done.

I have attached a shorts.lbr.  You can add packages with varying widths

of SMD pads as you feel appropriate, but it's a good example from which

to start.

I also had a similar problem where I wanted part of the plane to have islands and part of it to not have islands. In order to make some of the islands disappear I had to make extra polygons with different nets.

Lupo suggested creating multiple polygons for the same signal.  This is

a good way to achieve your goal in that you can control the

characteristics of each polygon separately.  i.e. You can turn Orphans

on for areas where you want islands, and off for areas where you don't

want islands.  But ALL the VDD polygons can have the same name.

I have also been know to place a wire in the tRestrict layer of as 1206

package to prevent copper fills underneath the part.  It's pretty easy

for a solder bridge to form under the part if you don't have a solder

mask (barebones board).

HTH,

    - Chuck

Wow, that was a really helpful answer!

Thanks so much Chuck, I will try some of these and post any questions I have. Thanks again, did not expect such a thorough response.

On 09/20/2012 11:49 PM, Jonathan Gordon wrote:

Wow, that was a really helpful answer!

 

Thanks so much Chuck, I will try some of these and post any questions I have. Thanks again, did not expect such a thorough response.

You're quite welcome.  I have found shorts to come in handy when I have

multiple ground signals (AGND and DGND) that need to be tied together at

a single "golden rivet".

Enjoy,

    - Chuck