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Removing overlap error from package

Former Member

I have created a package which has several pads which I want to be pre-connected with wire. The pre-connected pads show up fine in layout editor, but DRC check gives overlap errors. Is there a way to define that the pads and the wire are part of a same signal? In device editor I have already defined that the pads are connected.

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    Answering to myself: The overlap errors appear only when you put the component down without connecting any of the pins. Once you connect one pin to something, the overlap errors disappear. You can even connect one pin to itself and the errors disappear, or even just connect a dangling net which is not connected to anything. This is a workaround, because ideally I just want to put the bare component without connections to the board (test fixture).