Low plating index

On Thu, 23 May 2013 19:57:18 +0000, Matt Porta wrote:

Ok so I just got a issue back from my board house, I combined 5 pcbs in

one panel.

 

You can see the info in the uploaded picture. The plating index is low

and it need to bost it up. I understand I need to make the copper

distribtion move even (even though im not sure what 'even is') Am I

right in saying one way is to add copper traces which dont do anything

where I can on the board? Or I read somewhere that you can fill another

layer with copper or something like that. Only thing is im working with

eagle light so I only have two traces which Ive used both as much as

each other on all the boards.

 

 

Also where it says it may get brunted for instance where the redish

color is on that 10 pin header. That is because I had to ground 4 of the

pins, I dont think there is anyway round this as I need to keep it like

that. I also attached a zoomed in pic.

 

 

Could anyone take a look and tell me what is acctually bad and what

needs to be changed. And how I need to go about doing that on eagle.

 

Thanks!

 

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I dunno what this "plating index" stuff is.  You can always ask -- your

PCB vendor probably already knows you're a newbie, so asking naive but

intelligent questions will only raise their impression of you.

At a guess if you fill the areas between boards with a grid of traces

then your copper would be more even.  That may make them happy.

--

My liberal friends think I'm a conservative kook.

My conservative friends think I'm a liberal kook.

Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software

http://www.wescottdesign.com

Yeah, im just waiting for a reply back from them!

I think its pretty much about a even copper distrubtion. They said they will fill the areas between boards to even it out. But could you shed some light about how you would go about getting a even copper on a single pcb after the traces have been put down

On 24/05/13 13:13, Matt Porta wrote:

Yeah, im just waiting for a reply back from them!

 

I think its pretty much about a even copper distrubtion. They said they

will fill the areas between boards to even it out. But could you shed

some light about how you would go about getting a even copper on a

single pcb after the traces have been put down

 

The PCB house I use told me that they need a "similar" proportion of

copper vs. gap on all layers, but they were OK with a corner of the

board being very sparse on all layers when the rest of the board is

extensively flood-filled. It sounds like YMMV, though.

Rob

On Fri, 24 May 2013 12:13:13 +0000, Matt Porta wrote:

Yeah, im just waiting for a reply back from them!

 

I think its pretty much about a even copper distrubtion. They said they

will fill the areas between boards to even it out. But could you shed

some light about how you would go about getting a even copper on a

single pcb after the traces have been put down

After I autoroute a board, I define a pair of filled polygons on the top

and bottom, connected to ground.  I use a grid fill.  This will do a

pretty good job of filling up the board.

Then, if I'm even the least bit concerned about signal integrity, I

dribble ground-connected vias around the board to connect the top and

bottom fills (and if I'm feeling ambitious, to get more fill in empty

areas).

If you're autorouting, you want to do this AFTER you route -- otherwise

the autorouter will connect ground to the polygons, and slice up the

polygons.  If you've put down the polygons and you want to make changes

that include autorouting, the easiest thing I've found to do is to rename

the nets (to Bob, or Ralph -- anything that's not already a net name),

autoroute, then rename them to ground again.  If you did the via drop

thing then when you rip up everything to reroute you'll blow away the vias

and you'll have to redo.

--

My liberal friends think I'm a conservative kook.

My conservative friends think I'm a liberal kook.

Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software

http://www.wescottdesign.com

Thanks alot Tim this helped me alot. I do understand the cocept of what your saying, but trying to use in within a design ive allready layed down seems still a bit confusing.

So bascily this pcb here is causing me greif because of the amount on un used space on the far right. So bascily I have put in a polygon hatched in a big open space. I dont want to to do anything just to even out the copper.

Would what ive done here be suitable? Im just not sure how to add it to this pcb. I guess im pretty hestitant to add random traces via's etc as Im not sure where would be best and dont want to interfere with anything.

I attached the .brd file if you want to take a futher look and see what would be best!

Thanks again Tim

http://www.sendspace.com/file/pq5khc

Heres the .brd Its on sendspace because I couldnt attached directly in a reply!

On 05/28/2013 05:00 PM, Matt Porta wrote:

So bascily this pcb here is causing me greif because of the amount on un

used space on the far right. So bascily I have put in a polygon hatched

in a big open space. I dont want to to do anything just to even out the

copper.

 

Would what ive done here be suitable? Im just not sure how to add it to

this pcb. I guess im pretty hestitant to add random traces via's etc as

Im not sure where would be best and dont want to interfere with

anything.

I've never heard of a plating index, either.  It may have something to

do with the amount of time the board stays in the etching solution.

Areas with little copper will take more time to etch that areas with a

lot of copper?  It doesn't make sense, though, assuming that the entire

board is exposed to a homogeneous etching solution.  Frothing will not

only reduce the etching time, but it will also yield a more even etch

with less undercutting.

I'd like to understand exactly what a plating index is, how it plays in

the fabrication process, and why it's a design concern.

When you find out, I'd appreciate a post regarding this.

Thanks,

    - Chuck

Matt, et al.,

I think I just found a decent explanation of plating index.

Check out this article at eurocircuits

<http://www.eurocircuits.com/index.php/eurocircuits-printed-circuits-blog/plating-simulation-a-new-tool-for-pcb-designers>.

Rather than starting with a copper laminate panel and removing copper in

unwanted areas, they're starting with a bare fiberglass (for FR4) panel

and using galvanic copper deposition to add copper in wanted areas.

The problem focuses on the holes.  Overplating can result in the holes

closing up to a smaller than desired diameter.  Underplating risks thin

walls in the holes.

A low plating index means that your design has /more/ copper than the

average of the board and risk thin traces and hole walls.  To correct

this, you need to remove copper from that area, or increase the average

of the board by adding copper elsewhere.

A high plating index means that you have /less/ copper than the board's

average.  In these areas you need to add copper.

In your last post, adding a hatched polygon to the low plating index

area is exactly opposite what you need to do.

More specific to Matt's original problem, one solution may be to widen

your traces.  Even though they're carrying signal level currents, they

can be wider.  A wider trace can withstand more flexing of the board

when it's exposed to mechanical shock and vibration.

Another solution would be to change the hatched polygon to encompass the

entire board.  This would provide a more even distribution of copper

throughout the entire board.  If you name the polygon "GND", it will

connect to all the other GND signals.

HTH,

    - Chuck

On 05/29/2013 08:04 AM, Chuck Huber wrote:

On 05/28/2013 05:00 PM, Matt Porta wrote:

So bascily this pcb here is causing me greif because of the amount on un

used space on the far right. So bascily I have put in a polygon hatched

in a big open space. I dont want to to do anything just to even out the

copper.

 

Would what ive done here be suitable? Im just not sure how to add it to

this pcb. I guess im pretty hestitant to add random traces via's etc as

Im not sure where would be best and dont want to interfere with

anything.

I've never heard of a plating index, either.  It may have something to

do with the amount of time the board stays in the etching solution.

Areas with little copper will take more time to etch that areas with a

lot of copper?  It doesn't make sense, though, assuming that the entire

board is exposed to a homogeneous etching solution.  Frothing will not

only reduce the etching time, but it will also yield a more even etch

with less undercutting.

 

I'd like to understand exactly what a plating index is, how it plays in

the fabrication process, and why it's a design concern.

 

When you find out, I'd appreciate a post regarding this.

 

Thanks,

    - Chuck

 

On 05/29/2013 07:45 AM, Chuck Huber wrote:

Matt, et al.,

 

I think I just found a decent explanation of plating index.

 

Check out this article at eurocircuits

<http://www.eurocircuits.com/index.php/eurocircuits-printed-circuits-blog/plating-simulation-a-new-tool-for-pcb-designers>.

Rather than starting with a copper laminate panel and removing copper in

unwanted areas, they're starting with a bare fiberglass (for FR4) panel and

using galvanic copper deposition to add copper in wanted areas.

Close.  The panel starts out with a thin copper layer, much thinner than

the final copper thickness.  The panel is then given a negative mask,

leaving the desired traces exposed, and the exposed areas plated up to

the desired thickness.  Then the negative mask is removed, a positive

mask applied, and the undesired copper is etched away.  The advantage is

that only the thin initial layer needs to be removed by etching.

--

Bob Nichols         AT comcast.net I am "RNichols42"