How to apply net class to unconnected pad?

Hi,

I had the same trouble on some high voltage gate drivers (unconnected pin class). I don't have no other solution than your, and i would be glad if someone have a better solution...

Guillaume.

On 2/02/2015 9:06 p.m., Tomas Bergh wrote:

Hi all,

 

I would be glad to have some input on an issue I ran into recently:

 

Assume I added a diode in a sot23 package. The diode symbol only have

two (anode and cathode) connecting pins but the package has three pads.

To the two connecting pins I assign netclasses with different clearance

and creepage restrictions but then there will be no netclass assigned to

the third pad of the package. This generates tons of errors when running

drc and I dont have full control of the clearance and creepage

distances.

 

For the devices I create myself I can add a connecting pin for each pad

in the device and then add a short unconnected net to the unconnected

pads so that I can apply a netclass. This is not the correct way to do

it, does anyone know if is there any other way to do this?

You say you get "tons of errors" to this unconnected pad so I assume it

is a polygon pour that is getting too close to this unused pad. If this

is the case keep the polygon away by surrounding the pad with a fence

wires on the tRestrict layer.The width of the wire is at least the

clearance you require and should be close to but not touch the pad.

HTH

Warren

Hi,

No, I do not use a fill in the top layer here. The clearance issues of importance are between the unconnected pad (top right pad of D9) and the other two pads on the same sot23 package. (D9)

There are also clearance errors to other components in this example. (between T1, D7 and D9)

Any ideas?

Regards,

Tomas

Tomas,

There will not be a way to do this in the schematic since the

unconnected pin is not represented in the symbol.  I haven't found a way

to do this in the board, either.  But I can think of a couple of

workarounds.

It may seem like going around one's elbow to get to one's hand to solve

this, but there are ways.

First method, edit the connections on the device in the library and add

the unconnected pad to either the cathode or the anode.  Make sure the

connection type is "all", not "any".  The pro in this method is that the

pad assumes the same class as whatever net is connected to the

cathod/anode.  The con to this is that it has an impact on any design

that uses that device/package.  You'll have to route a trace from the

otherwise unconnected pad to one of the other two, but this shouldn't

have any impact since you won't have any unrelated traces threading

their way through a SOT23 (or at least shouldn't).

Second method would be to create a diode symbol that has an extra pin

named "NC".  Create a device (DIODE3 perhaps?) using this symbol and the

SOT23 package and connect appropriately.  The replace your diode in the

schematic with the DIODE3 device.  Now you have a way to assign a class

to the pin.  You also have a way to connect the NC pin to either the

cathode or the anode, whichever provides easier routing.

The caution in both of these methods is that you MUST be sure that the

unconnected pad on the diode is truly not connected to anything - not

even the substrate.

A third method is probably easiest - ditch the single diode and go with

a dual diode in a SOT23 - there might not be any price difference, and

if so, it's probably minimal.  You can choose which of the two diodes to

use based on ease of routing.  Whether or not a dual diode can be found

to fit your requirements and pricing is a design decision.

HTH,

    - Chuck

On 02/03/2015 02:02 AM, Tomas Bergh wrote:

Hi,

No, I do not use a fill in the top layer here. The clearance issue of

importance are between the unconnected pad (top right pad of D9) and the

other two pads on the same sot23 package. (D9)

There are also clearance errors to other components in this example.

(between T1, D7 and D9)

 

 

 

Any ideas?

 

Regards,

Tomas

 

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Hi,

Thanks for your effort Chuck and Warren. I am thankful.

I think the easiest workaround is just to approve the ERC-errors and check the clearance manually...

As the person I am I prefer it to be correct and this is the reason for asking here..

I just leave the thread as unsolved for now and maybe someone releases some proper solutions that actually solve this issue now or later.

Thanks,

Regards

Tomas

Hi,

On some special device (high voltage gate driver) I have this problem. I add a pin on the symbol for each unconnected pin. In schematic I draw a wire connected to this only pin and I set the class of this wire. I get 2 warning : One because I connect a "NC" pin, and a second because the wire is connected to only one pin....

This solution is not perfect because you still get 2 error to approve, but it's better for controlling polygon, and easier to approve 2 warning in schematic than several in board....

The perfect solution will be to let us define the class on unconnected pad in the board editor, but I guess that is for the 'suggestion forum. And IMO, this is not the most urgent, since there is a workaround.

Guillaume.

Hi Guillaume,

Yes, this is how I did earlier and it solves the issue but I would like to get around this without having to make a special device with pins for all pads.

Thanks,

/Tomas

Hi Thomas,

I don't have better solution, and I think that there is no better one with the today's eagle version.

The best way would be to be able to select a pad (in board editor) and change the class, or maybe in schematic editor a way to select the class of every unconnected pin of the package.. But it's not possible (for now).

Sorry !