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EAGLE User Support (English) Eagle PCB generates wire origins in top copper?
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Related

Eagle PCB generates wire origins in top copper?

rtmsllc
rtmsllc over 10 years ago

Hi there...can you please explain how to remove top copper origin and via X marks that have appeared in the top copper plot?  Thanks for any assistance!

RT

 

image

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  • autodeskguest
    0 autodeskguest over 10 years ago

    On 18/03/15 21:33, Robert Thomas wrote:

    Hi there...can you please explain how to remove top copper origin and

    via X marks that have appeared in the top copper plot?  Thanks for any

    assistance!

    RT

     

    That depends on how you're generating the plot.

     

    If you're using "print" or "export as PNG" or similar, then you need to

    deselect the tOrigins / tPlace / tDocu layers before doing so.

     

    If you're using the CAM processor (e.g. to make Gerber files) then you

    need to ensure that the relevant section of your CAM job doesn't include

    those layers.

     

     

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  • rtmsllc
    0 rtmsllc over 10 years ago in reply to autodeskguest

    Right, thanks....The only layers I have active in the in the CAM processor provided with 7.2.0 for OSX are 1, 17, 18 and 44/45 top, pads, vias, drills, holes.

     

    I also deactivated all the the other layers in PCB while looking at the .brd file...saved it with only these layers active....

     

    Weird, it is like center markers in tPlace got merged into the copper on 1...

     

    Any ideas??

     

    thank you,

     

    RT

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  • rtmsllc
    0 rtmsllc over 10 years ago in reply to autodeskguest

    Thanks again...of course having the drills and holes layers on generated these artifacts.  I was thinking that would generate the drl files which are subject to a separate process.  Fun learning Eagle, great tool for value.

     

    RT

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