I use Eagle 5.11 but the same is in 5.9 & 5.10.
I have designed a complex components with some layer 41(tRe) symbol.
When making my pcb I mirror the components so it is placed at the bottom
of my pcb. Right.
Then I use my *.ULP program to make a *.DNS file.
In the output when the components is placed at the bottom it all time
make restrict at the toplayer (41 tRe), and this is wrong, because I
have mirrored the components.
If I place the components at the top layer, then it generate the right
output in the *.DNS file!
If I in the lib.editor draw the layer 42(bRe) and then again place the
components at the bottom of the pcb, then it make the right *.DNS file.
Can it be right, I may draw both layer 41 & 42 in the lib.editor? It
give a lot of problem with running the DRC!!!