Actions
Forum Thread Details
  • Replies 6 replies
  • Subscribers 176 subscribers
  • Views 981 views
  • Users 0 members are here
Related

Via sizes increases when custom library com ponent added to PCB

autodeskguest

HI folks

 

Wonder if you can help. Although I am not a complete newbie to Eagle I

still have limited experience. I have completed double sided designs and

had them made using Gerbers..

 

However I am working on a PCB design uses some new parts which have taken

me into unknown territory.

 

I have created a library part for a QFN component and included links and

vias to take connections automatically to the underside layer. These need

to be very small as follows:

 

Tracks are 0.15 mm and vias are 0.45 mm dia. with 0.25 mm holes

 

Having created the part I then inserted the component in the normal way on

the PCB, however the vias are now much larger! They appear to have grown

and now badly overlap. I even went back to the library part to check the

via sizes which were of course as I had manually set them.

 

Having not gone down this low before for vias I am obviously missing

something important.

 

Can you help me see the error of my ways please

 

regards

Al

--

Browser access to CadSoft Support Forums at http://www.eaglecentral.ca

 

Parents

  • Al schrieb:

    HI folks

     

    Wonder if you can help. Although I am not a complete newbie to Eagle I

    still have limited experience. I have completed double sided designs and

    had them made using Gerbers..

     

    However I am working on a PCB design uses some new parts which have taken

    me into unknown territory.

     

    I have created a library part for a QFN component and included links and

    vias to take connections automatically to the underside layer. These need

    to be very small as follows:

     

    Tracks are 0.15 mm and vias are 0.45 mm dia. with 0.25 mm holes

     

    Having created the part I then inserted the component in the normal way on

    the PCB, however the vias are now much larger! They appear to have grown

    and now badly overlap. I even went back to the library part to check the

    via sizes which were of course as I had manually set them.

     

    Having not gone down this low before for vias I am obviously missing

    something important.

     

    Can you help me see the error of my ways please

     

    regards

    Al

     

     

    The 'vias' you set in the package editor actually are 'pads' and they

    have to follow the restring settings in the Design Rules. I suppose

    the minimum value for the copper ring arround the drilling is to high.

    Try to set it to 0.1mm and also check the value of the precentage.

    How Restring settings work can be read there:

      http://www.cadsoftusa.com/faq.htm.en#06012601

     

    HTH

    --

    Mit freundlichen Gruessen / Best regards

    Richard Hammerl

    CadSoft Support -- hotline@cadsoft.de

    FAQ: http://www.cadsoft.de/faq.htm

     

  • in reply to Richard_H

    So is there a way to create vias rather than pads in a package?

    or can one convert pads into vias?

     

    Or is it that vias are not supported inside packages at all.

     

    In which case the vias would have to be manually added after placement?

    Which would be true for BGA packages also yes?

     

    I am obviously a bit confused as I thought adding vias to high density

    packages to ease placement was a common industry practice?

     

    Unfortunately PCB manufacturers minimum pad sizes tend to be much higher

    than their minimum via sizes.

     

    regards

    Al

    --

    Browser access to CadSoft Support Forums at http://www.eaglecentral.ca

     

Reply
  • in reply to Richard_H

    So is there a way to create vias rather than pads in a package?

    or can one convert pads into vias?

     

    Or is it that vias are not supported inside packages at all.

     

    In which case the vias would have to be manually added after placement?

    Which would be true for BGA packages also yes?

     

    I am obviously a bit confused as I thought adding vias to high density

    packages to ease placement was a common industry practice?

     

    Unfortunately PCB manufacturers minimum pad sizes tend to be much higher

    than their minimum via sizes.

     

    regards

    Al

    --

    Browser access to CadSoft Support Forums at http://www.eaglecentral.ca

     

Children
No Data