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DRC Resting problem

Former Member

My understanding until now was that DRC:Resting could only force the pads'

rings to enlarge. However in my recent board I had to use 1mm pitch pin

header, which results in only 3mil rings around the holes. When added the

package to the board, the rings were quite fat, making them touch each

other. So I went to DRC and reduced RESTING:PADS:TOP and BOTTOM to 3mil. I

also had to reduce the "%" from the usual 25% to stop it from enlarging the

pads.

 

So far so good, but it also affected all of my other pads, giving them ALL

3mil rings! This is smaller than what those packages have spec'd in

libraries! Now, I understand 3mil is unreasonably small ring and I can

tolerate it on a debugging port which will see limited use and zero on

production boards, but I can't allow it on actual external connectors and

such.

 

How do I deal with that? I'm ok to have normal design rules for the rest of

the circuit and have DRC errors for this one header, but I can't seem to

have fat rings for all connectors, and think ring for this one.

 

See attached pic. On the left is the library, and on the right is the

board. DRC below.

 

Any help would be much appreciated.

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Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

 

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  • On 11/10/2016 3:51 a.m., Slava wrote:

    My understanding until now was that DRC:Resting could only force the pads'

    rings to enlarge. However in my recent board I had to use 1mm pitch pin

    header, which results in only 3mil rings around the holes. When added the

    package to the board, the rings were quite fat, making them touch each

    other. So I went to DRC and reduced RESTING:PADS:TOP and BOTTOM to 3mil. I

    also had to reduce the "%" from the usual 25% to stop it from enlarging the

    pads.

     

    So far so good, but it also affected all of my other pads, giving them ALL

    3mil rings! This is smaller than what those packages have spec'd in

    libraries! Now, I understand 3mil is unreasonably small ring and I can

    tolerate it on a debugging port which will see limited use and zero on

    production boards, but I can't allow it on actual external connectors and

    such.

     

    How do I deal with that? I'm ok to have normal design rules for the rest of

    the circuit and have DRC errors for this one header, but I can't seem to

    have fat rings for all connectors, and think ring for this one.

     

    See attached pic. On the left is the library, and on the right is the

    board. DRC below.

     

    Any help would be much appreciated.

     

     

    Hi

     

    Understand exactly how restrings are specified by having a read of the

    following:

      https://cadsoft.io/support/faq/#2

     

    With the reducing geometries of modern components and boards the only

    way forward is to not use 'Auto' as the pad diameter in the libraries

    and set the DRC restring settings such that you force the minimum

    restring which is usually the board house minimum. The % is set really

    low so the first calculation is below the minimum for the small drill.

    Hence they will be increased at least to the target minimum.

    If the specified diameter is greater, then that will be used.

     

    The upshot of this is that all your library pad diameters need to be

    specified.

     

    The Eagle supplied libraries have about 160,000 pads set to auto so

    always take your parts from a personalised library having set the pad

    diameters once.

     

    HTH

    Warren

     

     

     

     

     

     

     

  • in reply to autodeskguest

    Thank you very much, that works. I did not realize that AUTO diameter in

    library means it will be calculated solely based on DRC. I thought it is

    calculated and assigned in library.

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    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.