Have a question about CadSoft EAGLE?  Ask our Expert, Richard! (Archive)

Richard,

I'm down to only one mystery (at least until I make CAM files, which is tomorrow's adventure :-)  

On one of my boards DRC returns a Drill Size error on layer 20 for every via.  The vias are well away from the board edge and other drill holes and other components etc.  I don't get what it is seeing.  My other board does not do this yet the vias are the same size and the design rules are the same for both boards.  Do you know what it is complaining about with these errors?

Thanks - couldn't do it without you!

Mike

I see what it is doing now.  When the stop mask layers are on, it throws  a DRC error to anything that violates the stop mask - names, values,  place, origins.  Whatever is displayed in the image is tested against  the stop mask.  So see if there are any real stop mask violations, I'll  have to turn off all the layers that print or draw anything other than  top and bottom traces and vias and pads etc.

Maybe you defined a drill size value for net classes?

Regards,

Richard

Richard,

That's a good thought, but the only net class that exists is the default and width, drill, and clearance are all 0.

The via sizes, drill sizes, restring, and all design rules are the same on both boards.

Why is layer 20 involved?

Thanks,

Michael Watts

Richard,

That's a good thought, but the only net class that exists is the default and width, drill, and clearance are all 0.

The via sizes, drill sizes, restring, and all design rules are the same on both boards.

Why is layer 20 involved?

Thanks,

Michael Watts

Hi Michael,

I am glad to read that you got out what the problems were, and to be honset, I am glad that the problem was not an EAGLE fault.

All the best,

Richard

Richard,

I don't believe it either.  At this time both design rules sets min drill size less than I use and all is well.  I suspect pilot confusion:  I thought I set the min drill sizes in both sets of design rules to be the same but really didn't.  In fact when I went to the board that never showed the problem, the min drill size was set to 2mils.  I suspect I meant to type 23mils and dropped the 3 but thought it was really set to 23 mils.  All good, my fault, sorry.

On the .055 drills size problem:  I am using Excellon format and pointing it to the rack file createad by the ulp.  The problem was that it was just being pointed at the wrong rack file.  Eagle uses the directory in which the board file is located for everything except the rack file - which path has to be set manually.  Once I tumbled to that, and got it pointed to the correct rack file, it works fine. 

That's good info on the Excellon_rack format.  It would save a step and avoid the kind of error I made.  I'll try it out.

Your help has been invaluable!  The files are at the fab house now and, if the drill files are right this time (and they look ok), we are off to the races.  Thanks a ton, Richard!  You are welcome at my house any time!

Thanks,

Michael Watts

I think the min drill size was larger than some of the via holes.  I  used the .0193xxx drill size and the min drill size in the design rules  was 23 mils.  I made all the vias 20 mils and the min drill size 20 mils  and I get no errors now. 

Glad that this works now.

What's weird is that the min drill size in  the design rules for the ohter board I'm doing is also 23 mils and there  20 mil vias all over that board and it reports no drc errors.

Well, I can't believe that. If possible, pleae send me the board file, so I can check this.

My  current problem is:  a thru hole component's pads need 55 mil holes.   The drc reports no errors, but the CAM processor won't take that one  particular hole size.  In the .drl file generated by the ulp there is a  drill of .055.  Yet when I run the drill layer in the CAM processor it  says the .055 drill is missing.  I changed the hole size to a much  smaller size and it took it, but it won't take the .055 drill.  This is  not the largest hole size I call for - there are some .152 holes.  So I  don't have a clue why the CAM processor doesn't like that drill size.   Help!

Do you use the EXCELLON_RACK device for generating drill data? If yes, did you allow tolerances for reding the rack file? There should be set a +/- 2.5% tolerence.

What if you take EXCELLON. You don't have to run the ULP before, because EXCELLOn device wrties frill table and drill data in one common file.

Regards,

Richard

I think the min drill size was larger than some of the via holes.  I used the .0193xxx drill size and the min drill size in the design rules was 23 mils.  I made all the vias 20 mils and the min drill size 20 mils and I get no errors now.  What's weird is that the min drill size in the design rules for the ohter board I'm doing is also 23 mils and there 20 mil vias all over that board and it reports no drc errors.

My current problem is:  a thru hole component's pads need 55 mil holes.  The drc reports no errors, but the CAM processor won't take that one particular hole size.  In the .drl file generated by the ulp there is a drill of .055.  Yet when I run the drill layer in the CAM processor it says the .055 drill is missing.  I changed the hole size to a much smaller size and it took it, but it won't take the .055 drill.  This is not the largest hole size I call for - there are some .152 holes.  So I don't have a clue why the CAM processor doesn't like that drill size.  Help!

Thanks,

Mike

mike watts wrote:

 

Richard,

 

That's a good thought, but the only net class that exists is the default and width, drill, and clearance are all 0.

 

The via sizes, drill sizes, restring, and all design rules are the same on both boards.

 

Why is layer 20 involved?

 

Thanks,

 

Michael Watts

Drill size and Layer 20 belong together, because each drilling (the circumference) is drawn in layer 20.

We need it for example for the autorouter. It is a kind of border as the board contour is.

What are the actual values for min drill size in the Design Rules and the drill diameter of the vias?

Regards,

Richard