Have a question about CadSoft EAGLE?  Ask our Expert, Richard! (Archive)

Hi Richard,

I have a question about ULP.

Has I've found no such example on the web... I ask an Expert!

Is it possible to run a SCRIPT in a Board Editor Window, form an ULP that is running from the Schematic Editor Window?  And how?

Thank's

JG

Hey Richard,

I am trying to avoid running a long wire all around the screen. How can I accomplish a "supply symbol" part but with my own labels? Or simplying naming a wire and using that name later on? Thanks.

Hi Richard,

I have been using EAGLE probably as long as you and now notice when scouring the Farnell wwebsite that many components have an EAGLE library part that one may download.

I am always making new parts for Farnell components.

Is there a way for users to upload these parts for other Farnell / EAGLE customers to benefit from?

Thanks

Dave

Richard,

That's a good thought, but the only net class that exists is the default and width, drill, and clearance are all 0.

The via sizes, drill sizes, restring, and all design rules are the same on both boards.

Why is layer 20 involved?

Thanks,

Michael Watts

I see what it is doing now.  When the stop mask layers are on, it throws  a DRC error to anything that violates the stop mask - names, values,  place, origins.  Whatever is displayed in the image is tested against  the stop mask.  So see if there are any real stop mask violations, I'll  have to turn off all the layers that print or draw anything other than  top and bottom traces and vias and pads etc.

Maybe you defined a drill size value for net classes?

Regards,

Richard

Jason,

I see what it is doing now.  When the stop mask layers are on, it throws a DRC error to anything that violates the stop mask - names, values, place, origins.  Whatever is displayed in the image is tested against the stop mask.  So see if there are any real stop mask violations, I'll have to turn off all the layers that print or draw anything other than top and bottom traces and vias and pads etc.

Mike

Richard,

I'm down to only one mystery (at least until I make CAM files, which is tomorrow's adventure :-)  

On one of my boards DRC returns a Drill Size error on layer 20 for every via.  The vias are well away from the board edge and other drill holes and other components etc.  I don't get what it is seeing.  My other board does not do this yet the vias are the same size and the design rules are the same for both boards.  Do you know what it is complaining about with these errors?

Thanks - couldn't do it without you!

Mike

You're right there. I was just giving an explanation as to why they'd appeared, and if you wanted it to be back as it was before, then how you'd go about it.

I remember the first time I enabled the Stop layers, and was astounded how many DRC errors there were.

Luckily (?) I make my own PCBs, so I don't have a silk screen to worry about

Although technically you should respect the DRC errors....and move the

silkscreen where you can.

The whole philosophy of DRC is to let the software do the work of finding

problems.

At times of course it's too much work to adjust or make corrections (like

when a silkscreen in a part crosses over some other element, but the use of

keepouts and restricts are supposed to make your job better.

Do the names cross pads (SMT and PTH)? If so, then a DRC error will occur. There's another pair of layers which have been enabled which causes these DRC errors - I can't remember which layers they are though.

Although a quick manual test on an examle board suggests it's _tStop and _bStop. Hide those layers, and the DRCs for them should disappear.